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1. 发明申请

US20100191942A1 Information processor and control method 失效
标题翻译：信息处理器和控制方法
公开(公告)号：US20100191942A1
公开(公告)日：2010-07-29
申请号：US12659896
申请日：2010-03-24
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F9/30
CPC分类号： G06F11/1658 , G06F11/165 , G06F11/1679 , G06F2201/81
摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
摘要翻译：北桥在检测到冗余CPU的同步中断时，停止发生错误的异常CPU总线的运行，FWH中的固件指示北桥禁止外部指令。此外，固件还保存连接到普通CPU总线的正常CPU的内部信息，并将存储器上的数据缓存，并将北桥问题重置到家庭系统板中的所有CPU。然后，固件将CPU的内部信息恢复到所有CPU的存储器上，并指示北桥取消对外部指令的禁止。

2. 发明申请

US20080046695A1 System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function 有权
标题翻译：系统控制器，相同地址请求排队防止方法和具有相同地址请求排队防止功能的信息处理装置
公开(公告)号：US20080046695A1
公开(公告)日：2008-02-21
申请号：US11790266
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F13/1642
摘要： In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.
摘要翻译：在包括CPU发出的请求队列的系统控制器中，具有处理具有相同地址的多个请求的电路不被输入到CPU发出的请求队列，除了高速缓存替换请求以外的最新请求被保留部分。因此，即使发出的请求高速缓存替换请求的地址与CPU发出的请求队列所保留的请求的地址相匹配，也不会重新发出对高速缓存替换请求的发出请求，而是在CPU发出的请求队列中排队当发出的缓存替换请求的地址与输入请求保留部分保留的整个地址不匹配时。

3. 发明申请

US20080046663A1 System controller, snoop tag modification method and information processing apparatus having snoop tag modificaton function 有权
标题翻译：系统控制器，snoop标签修改方法和具有snoop标签修改功能的信息处理设备
公开(公告)号：US20080046663A1
公开(公告)日：2008-02-21
申请号：US11790263
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831
摘要： In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.
摘要翻译：在多处理器系统中，系统控制器包括窥探标签，这些标签是由各个CPU保留的缓存标签上的复制信息。如果在连接到同一CPU总线的每个CPU的缓存标签中的S（共享状态）中登记相同的地址，则只在与CPU对应的任何一个snoop标签中的S（共享状态）中注册该地址其中注册了相同的地址。

4. 发明授权

US08607103B2 Transmission/reception device, transmission device, reception device, and data transmission/reception method 失效
标题翻译：发送/接收设备，发送设备，接收设备和数据发送/接收方法
公开(公告)号：US08607103B2
公开(公告)日：2013-12-10
申请号：US13224995
申请日：2011-09-02
申请人： Takeshi Owaki , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
发明人： Takeshi Owaki , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
IPC分类号： G01R31/28
CPC分类号： G06F11/277
摘要： A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.
摘要翻译：发送/接收装置包括：将多条连接线划分为多个组的发送装置，确定多个组中的对应连接线，确定测试模式与连接线的对应关系，并将测试模式输出到基于测试图案和连接线之间的对应关系的多个连接线以及从发送装置接收测试图案的接收装置比较通过多个对应连接线接收的测试图案的相同位置中的比特基于测试图案和连接线之间的对应关系，并且基于比较结果，生成指示错误连接线的错误连接线信息作为连接线，其中已经在多条连接线中发生错误。

5. 发明授权

US08391184B2 Method of updating routing table, data transfer apparatus, and program 失效
标题翻译：更新路由表，数据传输装置和程序的方法
公开(公告)号：US08391184B2
公开(公告)日：2013-03-05
申请号：US12846175
申请日：2010-07-29
申请人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
发明人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , G06F21/6209 , G06F2221/2141 , H04L45/02
摘要： A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.
摘要翻译：更新路由表的方法包括：从发布源节点接收包括用于更新路由表的更新数据的写包; 基于写入包的内容，尝试识别包含发行源节点的分区; 基于（1）是否识别包括源节点的分区，以及（2）更新数据中的端口信息和分区信息是否存储在路由表中，确定是否允许更新路由表; 并且在允许更新时更新路由表。

6. 发明授权

US08065566B2 Node device, control device, control method and control program 有权
标题翻译：节点装置，控制装置，控制方法和控制程序
公开(公告)号：US08065566B2
公开(公告)日：2011-11-22
申请号：US11785759
申请日：2007-04-19
申请人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F11/10
CPC分类号： H04L1/004 , H04L1/0082 , H04L2001/0097
摘要： A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.
摘要翻译：管理发送和接收包含纠错码的数据的多个节点的控制装置包括当任何一个节点从包含纠错码的数据中检测到不可校正的错误时，接收由检测到错误的节点发送的信号从第一节点接收到的数据接收来自第二节点的信号，从第一节点的检测记录中判断第一节点是否从发送到第二节点的数据检测到不可校正的错误，并且意味着当第一节点从发送到第二节点的数据中检测到不可校正的错误时，停止归因于来自第二节点的信号的接受的处理。

7. 发明授权

US07873789B2 System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function 有权
标题翻译：系统控制器，相同地址请求排队防止方法和具有相同地址请求排队防止功能的信息处理装置
公开(公告)号：US07873789B2
公开(公告)日：2011-01-18
申请号：US11790266
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1642
摘要： In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.
摘要翻译：在包括CPU发出的请求队列的系统控制器中，具有处理具有相同地址的多个请求的电路不被输入到CPU发出的请求队列，除了高速缓存替换请求以外的最新请求被保留部分。因此，即使发出的请求高速缓存替换请求的地址与CPU发出的请求队列所保留的请求的地址相匹配，也不会重新发出对高速缓存替换请求的发出请求，而是在CPU发出的请求队列中排队当发出的缓存替换请求的地址与输入请求保留部分保留的整个地址不匹配时。

8. 发明授权

US07800396B2 Semiconductor integrated circuit, control method, and information processing apparatus 有权
标题翻译：半导体集成电路，控制方法和信息处理装置
公开(公告)号：US07800396B2
公开(公告)日：2010-09-21
申请号：US12475480
申请日：2009-05-30
申请人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Takeshi Owaki , Atsushi Morosawa
发明人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Takeshi Owaki , Atsushi Morosawa
IPC分类号： H03K19/003
CPC分类号： G01R31/31708 , G01R31/3004 , G01R31/31721
摘要： A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector.
摘要翻译：半导体集成电路包括经由总线连接到算术处理单元的电路块，电源噪声数据发生器，其被配置为通过转换电源的电源电压中产生的电源噪声来产生电源噪声数据信号，电路块，被配置为检测从电路块输出到总线的数据的错误的误差检测器，以及配置为基于电源噪声数据信号将电源噪声信息与总线上的数据相关联的写入控制器并将数据写入存储单元，并且响应于错误检测器的错误检测停止写入数据。

9. 发明申请

US20080046656A1 Multiprocessor system, system board, and cache replacement request handling method 有权
标题翻译：多处理器系统，系统板和缓存替换请求处理方法
公开(公告)号：US20080046656A1
公开(公告)日：2008-02-21
申请号：US11790265
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/12 , G06F15/76
CPC分类号： G06F12/0833
摘要： A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.
摘要翻译：通过CPU总线和CPU发出的请求队列，从本地仲裁器输出CPU发出的请求。高速缓存替换请求环回电路在环回确定电路中确定输出的请求是否是高速缓存替换请求。除了缓存替换请求之外的请求被输出到本地总线上。当全局总线上没有有效请求时，高速缓存替换请求被输出到选择器并发送到请求处理部分。

10. 发明授权

US08458551B2 Verification device, verification method, and verification program 失效
标题翻译：验证设备，验证方法和验证程序
公开(公告)号：US08458551B2
公开(公告)日：2013-06-04
申请号：US12926218
申请日：2010-11-02
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Takashi Yamamoto , Atsushi Morosawa
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Takashi Yamamoto , Atsushi Morosawa
IPC分类号： H04L1/18 , G08C25/02
CPC分类号： H04L1/0061 , H04L1/0006 , H04L1/0009 , H04L1/0025 , H04L1/0075 , H04L1/008 , H04L1/18 , H04L1/245 , H04L69/324
摘要： A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.
摘要翻译：验证装置包括数据验证单元，其使用第一或第二验证模式验证分组中的数据是否具有错误;分组生成单元，分别根据第一分组生成模式或第二分组生成模式生成分组对应于第一和第二验证模式的故障监视单元，监视需要切换验证模式的传输线路的故障的故障监视单元，向目的地设备发送用于通知切换的切换分组的切换分组发送单元当故障监视单元检测到故障或故障消除时由数据验证单元使用的验证模式，切换生成模式的生成模式切换单元和将验证模式切换到一个的验证模式切换单元由切换包通知。

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