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1. 发明授权

US10964355B2 Memory device with strap cells 有权
公开(公告)号：US10964355B2
公开(公告)日：2021-03-30
申请号：US16744076
申请日：2020-01-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Jonathan Tsung-Yung Chang , Cheng-Hung Lee , Chi-Ting Cheng , Hung-Jen Liao , Jhon-Jhy Liaw , Yen-Huei Chen
IPC分类号： G11C5/02 , G11C5/14 , G11C7/10 , G11C7/12 , G11C11/417 , G11C7/22
摘要： A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.

2. 发明申请

US20200075092A1 MEMORY READ STABILITY ENHANCEMENT WITH SHORT SEGMENTED BIT LINE ARCHITECTURE 审中-公开
公开(公告)号：US20200075092A1
公开(公告)日：2020-03-05
申请号：US16676850
申请日：2019-11-07
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Mahmut Sinangil , Hidehiro Fujiwara , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Sahil Preet Singh
IPC分类号： G11C11/419 , G11C7/18 , G11C8/16 , G11C7/16 , G11C11/412 , G11C8/12
摘要： In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

3. 发明授权

US10304500B2 Power switch control for dual power supply 有权
公开(公告)号：US10304500B2
公开(公告)日：2019-05-28
申请号：US15902118
申请日：2018-02-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687 , H03K17/22
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

4. 发明授权

US10204660B2 Memory device with strap cells 有权
公开(公告)号：US10204660B2
公开(公告)日：2019-02-12
申请号：US15831332
申请日：2017-12-04
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Jonathan Tsung-Yung Chang , Cheng-Hung Lee , Chi-Ting Cheng , Hung-Jen Liao , Jhon-Jhy Liaw , Yen-Huei Chen
IPC分类号： G11C5/02 , G11C5/14 , G11C7/10 , G11C7/12 , G11C11/417 , G11C7/22
摘要： A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is arranged across the first sub-bank. The second portion is arranged across the second sub-bank, and is coupled to the first portion via the first strap cell.

5. 发明授权

US09762216B1 Level shifter circuit using boosting circuit 有权
公开(公告)号：US09762216B1
公开(公告)日：2017-09-12
申请号：US15065166
申请日：2016-03-09
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Mahmut Sinangil , Hsin-Hsin Ko , Chiting Cheng , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： H03L5/00 , H03K3/356 , H03K19/0185
CPC分类号： H03K3/356113 , H03K19/018521
摘要： A level shifter circuit is provided that uses a boosting circuit. The boosting circuit is configured to improve the operation of the level shifter circuit when the high voltages of voltage domains across the level shifter circuit are widely separated. A circuit apparatus includes a core level shifter circuit that changes a first voltage of an input signal to a second voltage of an output signal. The circuit apparatus further includes a first boosting circuit that is coupled to the core level shifter circuit and generates a first transient voltage applied to the core level shifter circuit when the input signal transitions from a low value to a high value. The circuit apparatus also includes a second boosting circuit that is coupled to the core level shifter circuit and generates a second transient voltage applied to the core level shifter circuit when the input signal transitions from a high value to a low value.

6. 发明授权

US09601162B1 Memory devices with strap cells 有权
公开(公告)号：US09601162B1
公开(公告)日：2017-03-21
申请号：US15153687
申请日：2016-05-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Jonathan Tsung-Yung Chang , Cheng-Hung Lee , Chi-Ting Cheng , Hung-Jen Liao , Jhon-Jhy Liaw , Yen-Huei Chen
IPC分类号： G11C8/00 , G11C5/02 , G11C5/14 , G11C7/22 , G11C7/10
CPC分类号： G11C5/02 , G11C5/025 , G11C5/14 , G11C7/10 , G11C7/1069 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/417
摘要： A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.

7. 发明授权

US09183341B2 Pre-colored methodology of multiple patterning 有权
标题翻译：多色图案的预色方法
公开(公告)号：US09183341B2
公开(公告)日：2015-11-10
申请号：US14218001
申请日：2014-03-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout features including a plurality of word lines and a plurality of Y-control lines. A pre-coloring element pre-colors one or more of the plurality of word lines and Y-control lines, to indicate that pre-colored word lines and Y-control lines are to be formed on a same mask of a multiple mask set used for a multiple patterning lithography process. A decomposition element assigns different colors to uncolored layout features of the memory circuit, to indicate that different colored memory features are to be formed on different masks of the multiple mask set.
摘要翻译：一些实施例涉及对存储器单元内的字线和控制线进行预色彩以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟的系统。该系统具有存储图形IC布局的存储元件，其具有包括多个字线和多个Y控制线的布局特征的存储器电路。预着色元件对多个字线和Y控制线中的一个或多个进行预色，以指示预先着色的字线和Y控制线将被形成在所使用的多个掩模集的相同掩模上用于多重图案化光刻工艺。分解元素将不同的颜色分配给存储器电路的未着色布局特征，以指示将在多个掩模集合的不同掩模上形成不同的彩色存储器特征。

8. 发明授权

US10854282B2 Memory read stability enhancement with short segmented bit line architecture 有权
公开(公告)号：US10854282B2
公开(公告)日：2020-12-01
申请号：US16676850
申请日：2019-11-07
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Mahmut Sinangil , Hidehiro Fujiwara , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Sahil Preet Singh
IPC分类号： G11C11/419 , G11C11/412 , G11C7/16 , G11C7/18 , G11C8/12 , G11C8/16
摘要： In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

9. 发明授权

US10685686B2 Power switch control for dual power supply 有权
公开(公告)号：US10685686B2
公开(公告)日：2020-06-16
申请号：US16582029
申请日：2019-09-25
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687 , H03K17/22
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

10. 发明申请

US20190108874A1 MEMORY READ STABILITY ENHANCEMENT WITH SHORT SEGMENTED BIT LINE ARCHITECTURE 审中-公开
公开(公告)号：US20190108874A1
公开(公告)日：2019-04-11
申请号：US16211589
申请日：2018-12-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Mahmut Sinangil , Hidehiro Fujiwara , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Sahil Preet Singh
IPC分类号： G11C11/419 , G11C7/18 , G11C8/16 , G11C11/412 , G11C8/12 , G11C7/16
CPC分类号： G11C11/419 , G11C7/16 , G11C7/18 , G11C8/12 , G11C8/16 , G11C11/412 , G11C2207/005
摘要： In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

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