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1. 发明授权

US11264066B2 Leakage pathway prevention in a memory storage device 有权
公开(公告)号：US11264066B2
公开(公告)日：2022-03-01
申请号：US16999867
申请日：2020-08-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shang-Chi Wu , Cheng Hung Lee , Chien-Kuo Su , Chiting Cheng , Yu-Hao Hsu , Yangsyu Lin
IPC分类号： G11C7/22 , G11C7/10 , G11C7/12
摘要： The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.

2. 发明授权

US11200924B2 Method of minimizing read-disturb-write effect of SRAM circuit and SRAM circuit thereof 有权
公开(公告)号：US11200924B2
公开(公告)日：2021-12-14
申请号：US16876138
申请日：2020-05-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Jui-Che Tsai , Chia-En Huang , Yu-Hao Hsu , Yih Wang
IPC分类号： G11C7/10 , G11C7/12 , G11C7/06
摘要： In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

3. 发明授权

US10685686B2 Power switch control for dual power supply 有权
公开(公告)号：US10685686B2
公开(公告)日：2020-06-16
申请号：US16582029
申请日：2019-09-25
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687 , H03K17/22
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

4. 发明授权

US09007859B2 Far end resistance tracking design with near end pre-charge control for faster recovery time 有权
标题翻译：远端电阻跟踪设计，具有近端预充电控制，可实现更快的恢复时间
公开(公告)号：US09007859B2
公开(公告)日：2015-04-14
申请号：US14316857
申请日：2014-06-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chen-Lin Yang , Chung-Yi Wu , Yu-Hao Hsu
IPC分类号： G11C7/00 , G11C8/00 , G11C7/12 , G11C7/22 , G11C8/18 , G11C11/413
CPC分类号： G11C7/12 , G11C7/227 , G11C8/18 , G11C11/413
摘要： A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.
摘要翻译：公开了一种字线跟踪电路和相应的方法，并且包括具有与之相关联的阻抗特性的跟踪字线，其对存储器件中的一行存储器单元进行建模，其中跟踪字线行具有近端，其接收具有近端上升脉冲沿和近端下降脉冲沿。跟踪字线也有一个远端。跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。最后，电路包括耦合到跟踪单元的跟踪位线预充电电路，其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。

5. 发明授权

US11087833B2 Power management circuit in memory device 有权
公开(公告)号：US11087833B2
公开(公告)日：2021-08-10
申请号：US16907328
申请日：2020-06-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chia-Chen Kuo , Cheng-Hung Lee , Chi-Ting Cheng , Hua-Hsin Yu , Wei-Jer Hsieh , Yu-Hao Hsu , Yang-Syu Lin , Che-Ju Yeh
IPC分类号： G11C5/14 , G11C11/417 , G11C11/412
摘要： A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

6. 发明申请

US20210125662A1 POWER MANAGEMENT CIRCUIT IN MEMORY DEVICE 有权
公开(公告)号：US20210125662A1
公开(公告)日：2021-04-29
申请号：US16907328
申请日：2020-06-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chia-Chen Kuo , Cheng-Hung Lee , Chi-Ting Cheng , Hua-Hsin Yu , Wei-Jer Hsieh , Yu-Hao Hsu , Yang-Syu Lin , Che-Ju Yeh
IPC分类号： G11C11/417 , G11C11/412
摘要： A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

7. 发明授权

US10304500B2 Power switch control for dual power supply 有权
公开(公告)号：US10304500B2
公开(公告)日：2019-05-28
申请号：US15902118
申请日：2018-02-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687 , H03K17/22
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

8. 发明申请

US20170040042A1 Power Management Circuit for an Electronic Device 有权
标题翻译：电子设备电源管理电路
公开(公告)号：US20170040042A1
公开(公告)日：2017-02-09
申请号：US14980287
申请日：2015-12-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hektor Huang , Yangsyu Lin , Yu-Hao Hsu , Chia-En Huang , Chiting Cheng , Chen-Lin Yang , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： G11C5/14 , H02J4/00
CPC分类号： G11C5/147 , H02J4/00
摘要： A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.
摘要翻译：公开了一种用于电子设备的电源管理电路，其顺序地激活和/或去激活电子设备的电子电路。功率管理电路提供第一组一个或多个电路功率管理信号以激活和/或去激活来自电子电路之间的第一电子电路。此后，电源管理电路从一个或多个电路电源管理信号的第二组中提供相应的功率管理信号，其对应于已经被第一组的第一组激活和/或去激活的第一电子电路的一部分一个或多个电路功率管理信号，用于激活和/或去激活来自电子电路的第二电子电路的一部分。功率管理电路以类似的方式继续顺序提供一个或多个电路功率管理信号中的每一个，直到电子设备的电子电路已经被激活和/或去激活为止。

9. 发明授权

US09111595B2 Memory device with tracking wordline voltage level circuit and method 有权
标题翻译：具有跟踪字线电压电平电路和方法的存储器件
公开(公告)号：US09111595B2
公开(公告)日：2015-08-18
申请号：US13904653
申请日：2013-05-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yu-Hao Hsu , Ming-Chien Tsai , Chen-Lin Yang
IPC分类号： G11C8/08 , G11C7/06 , G11C7/12 , G11C11/419 , G11C29/50 , G11C29/52
CPC分类号： G11C8/08 , G11C7/06 , G11C7/12 , G11C11/419 , G11C29/50 , G11C29/52
摘要： A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.
摘要翻译：存储器包括响应于第二时钟信号和反馈信号提供第一时钟信号的时钟发生器。反馈回路提供反馈信号，并且包括跟踪字线，跟踪位线，跟踪位单元和用于响应于第一时钟信号驱动跟踪字线的跟踪字线驱动器。存储器包括跟踪字线电平调谐器，用于响应弱位控制信号减小跟踪字线上的跟踪字线信号的电压电平。

10. 发明申请

US20140307502A1 Far End Resistance Tracking Design with Near End Pre-Charge Control for Faster Recovery Time 有权
标题翻译：具有近端预充电控制的远端电阻跟踪设计，实现更快的恢复时间
公开(公告)号：US20140307502A1
公开(公告)日：2014-10-16
申请号：US14316857
申请日：2014-06-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chen-Lin Yang , Chung-Yi Wu , Yu-Hao Hsu
IPC分类号： G11C7/12 , G11C11/413
CPC分类号： G11C7/12 , G11C7/227 , G11C8/18 , G11C11/413
摘要： A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.
摘要翻译：公开了一种字线跟踪电路和相应的方法，并且包括具有与之相关联的阻抗特性的跟踪字线，其对存储器件中的一行存储器单元进行建模，其中跟踪字线行具有近端，其接收具有近端上升脉冲沿和近端下降脉冲沿。跟踪字线也有一个远端。跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。最后，电路包括耦合到跟踪单元的跟踪位线预充电电路，其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。

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