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1. 发明授权

US11411571B2 Phase-locked loop monitor circuit 有权
公开(公告)号：US11411571B2
公开(公告)日：2022-08-09
申请号：US17330818
申请日：2021-05-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
IPC分类号： H03L7/06 , H03L7/07 , H03L7/23 , H03L7/091 , H03L7/095 , H03K19/21
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

2. 发明授权

US10985922B2 Device with self-authentication 有权
公开(公告)号：US10985922B2
公开(公告)日：2021-04-20
申请号：US15907190
申请日：2018-02-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Haohua Zhou , Sandeep Kumar Goel
IPC分类号： G06F12/14 , G06F11/30 , H04L9/32 , H04L9/08
摘要： A device includes a first memory circuit, a second memory circuit and a processing circuit. The memory circuit is configured to store a distinguishable identification (ID). The second memory circuit is configured to store first hash data, wherein the first hash data is generated according to the distinguishable ID. The processing circuit is configured to generate second hash data according to the distinguishable ID when the device is powered on, and to compare the first hash data and the second hash data to determine whether the second hash data matches the first hash data.

3. 发明授权

US10371751B2 Circuit and method for diagnosing scan chain failures 有权
公开(公告)号：US10371751B2
公开(公告)日：2019-08-06
申请号：US15730411
申请日：2017-10-11
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/3185 , G01R31/3177
摘要： A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.

4. 发明授权

US10345883B2 Power estimation 有权
公开(公告)号：US10345883B2
公开(公告)日：2019-07-09
申请号：US15169635
申请日：2016-05-31
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Kai-Yuan Ting , Shereef Shehata , Tze-Chiang Huang , Sandeep Kumar Goel , Mei Wong , Yun-Han Lee
IPC分类号： G06F9/00 , G06F1/3228 , G06F1/28
摘要： A power state transformer, a system and a method thereof are disclosed. The power state transformer is coupled with a processing unit model. The power state transformer is configured for counting performance activities executed in the processing unit model, and further for determining a power state of the processing unit model according to count values of the performance activities.

5. 发明授权

US10256828B2 Phase-locked loop monitor circuit 有权
公开(公告)号：US10256828B2
公开(公告)日：2019-04-09
申请号：US15711201
申请日：2017-09-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
IPC分类号： H03L7/06 , H03L7/07 , G06F1/08 , H03L7/23 , H03L7/091 , H03L7/095 , H03K19/21
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

6. 发明授权

US09811627B2 Method of component partitions on system on chip and device thereof 有权
公开(公告)号：US09811627B2
公开(公告)日：2017-11-07
申请号：US14963151
申请日：2015-12-08
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Yung-Chin Hou , Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , G06F17/50 , H01L21/48 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/528 , H01L25/065 , H01L25/00
CPC分类号： G06F17/5072 , G06F17/5077 , H01L21/486 , H01L21/76883 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/49838 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548
摘要： A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.

7. 发明授权

US09646128B2 System and method for validating stacked dies by comparing connections 有权
公开(公告)号：US09646128B2
公开(公告)日：2017-05-09
申请号：US14705021
申请日：2015-05-06
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Ashok Mehta , Stanley John , Kai-Yuan Ting , Sandeep Kumar Goel , Chao-Yang Yeh
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/50 , G06F17/5072 , G06F17/5077 , G06F2217/78
摘要： A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

8. 发明授权

US09341672B2 Method and apparatus for interconnect test 有权
标题翻译：用于互连测试的方法和装置
公开(公告)号：US09341672B2
公开(公告)日：2016-05-17
申请号：US13864492
申请日：2013-04-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sandeep Kumar Goel , Saman M. I. Adham
IPC分类号： G11C29/00 , G06F11/00 , G01R31/317 , G11C29/50
CPC分类号： G01R31/31717 , G01R31/2856 , G01R31/3177 , G11C29/50
摘要： A method of testing interconnected dies can include forming a cell for the interconnected dies, applying at least a first input to the cell to perform an open or short defects test, and applying at least a second input to the cell to perform one or more of a resistive defects test or a burn-in-test. Test circuitry for testing an interconnection between interconnected dies can include a wrapper cell embedded within a die where the wrapper cell includes a scannable data storage element, a hold data module, a selection logic, a transition generation module, and one or more additional input ports for receiving inputs causing the wrapper cell to perform an open or short defects test in a first mode and causing the wrapper cell to perform one or more of a resistive defects test in a second mode or a burn-in-test in a third mode.
摘要翻译：测试相互连接的管芯的方法可以包括形成用于互连管芯的单元，将至少第一输入端施加到单元以执行开放或短缺陷测试，以及将至少第二输入施加到单元以执行以下步骤中的一个或多个电阻缺陷测试或老化测试。用于测试互连裸片之间的互连的测试电路可以包括嵌入在芯片内的封装单元，其中封装单元包括可扫描数据存储元件，保持数据模块，选择逻辑，转换生成模块以及一个或多个附加输入端口用于接收使所述包装单元在第一模式中执行打开或短缺陷测试的输入，并且使得所述包装单元在第三模式中执行在第二模式或老化测试中的电阻缺陷测试中的一个或多个。

9. 发明授权

US09194913B2 Circuit and method for diagnosing scan chain failures 有权
标题翻译：用于诊断扫描链失败的电路和方法
公开(公告)号：US09194913B2
公开(公告)日：2015-11-24
申请号：US14033536
申请日：2013-09-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/3185 , G01R31/3177
CPC分类号： G01R31/318541 , G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318561
摘要： A circuit includes a plurality of scan chains each including a plurality of scan blocks. Each scan block includes a storage element and a switching device having an output directly coupled to an input of the storage element. The switching device has a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed and a second input configured to receive one of a function logic output signal or a scan input signal. The switching device is configured to selectively couple the first input or the second input to the input of the storage element.
摘要翻译：电路包括多个扫描链，每条扫描链包括多个扫描块。每个扫描块包括存储元件和具有直接耦合到存储元件的输入的输出的开关器件。开关装置具有第一输入，其被配置为接收来自与其中设置开关装置的扫描链不同的扫描链中的存储元件的输出，以及被配置为接收功能逻辑输出信号或扫描输入中的一个的第二输入信号。开关装置被配置为将第一输入或第二输入选择性地耦合到存储元件的输入。

10. 发明申请

US20180364783A1 DYNAMIC FREQUENCY SCALING 审中-公开
公开(公告)号：US20180364783A1
公开(公告)日：2018-12-20
申请号：US16111881
申请日：2018-08-24
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kai-Yuan Ting , Ashok Mehta , Stanley John , Sandeep Kumar Goel
IPC分类号： G06F1/32
摘要： A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.

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