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1. 发明申请

US20160195807A1 Lithography Process on High Topology Features 审中-公开
标题翻译：高拓扑特征的平版印刷工艺
公开(公告)号：US20160195807A1
公开(公告)日：2016-07-07
申请号：US15067937
申请日：2016-03-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chun-Wei Chang , Hong-Da Lin , Chih-Chien Wang , Chun-Chang Chen , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： G03F7/00 , G03F7/20 , G03F7/32 , G03F7/16
CPC分类号： G03F7/0035 , G03F7/091 , G03F7/16 , G03F7/20 , G03F7/32
摘要： A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.
摘要翻译：一种方法包括在基底结构之上形成第一光致抗蚀剂层，在基底结构上形成目标特征，在第一光致抗蚀剂层上进行未图案化曝光，以及显影第一光刻胶层。在显影步骤之后，第一光致抗蚀剂层的角部保留在基底结构的顶表面和目标特征的边缘之间的角落处。在目标特征，基底结构和第一光致抗蚀剂层的角部上形成第二光致抗蚀剂层。使用图案化光刻掩模曝光第二光致抗蚀剂层。图案化第二光致抗蚀剂层以形成图案化的光刻胶。

2. 发明授权

US09285677B2 Lithography process on high topology features 有权
标题翻译：高拓扑特征的平版印刷工艺
公开(公告)号：US09285677B2
公开(公告)日：2016-03-15
申请号：US14071890
申请日：2013-11-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chun-Wei Chang , Hong-Da Lin , Chih-Chien Wang , Chun-Chang Chen , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： G03F7/26 , G03F7/00 , G03F7/09
CPC分类号： G03F7/0035 , G03F7/091 , G03F7/16 , G03F7/20 , G03F7/32
摘要： A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.
摘要翻译：一种方法包括在基底结构之上形成第一光致抗蚀剂层，在基底结构上形成目标特征，在第一光致抗蚀剂层上进行未图案化曝光，以及显影第一光刻胶层。在显影步骤之后，第一光致抗蚀剂层的角部保留在基底结构的顶表面和目标特征的边缘之间的角落处。在目标特征，基底结构和第一光致抗蚀剂层的角部上形成第二光致抗蚀剂层。使用图案化光刻掩模曝光第二光致抗蚀剂层。图案化第二光致抗蚀剂层以形成图案化的光刻胶。

3. 发明申请

US20140272715A1 Lithography Process on High Topology Features 有权
标题翻译：高拓扑特征的平版印刷工艺
公开(公告)号：US20140272715A1
公开(公告)日：2014-09-18
申请号：US14071890
申请日：2013-11-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chun-Wei Chang , Hong-Da Lin , Chih-Chien Wang , Chun-Chang Chen , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： G03F7/00
CPC分类号： G03F7/0035 , G03F7/091 , G03F7/16 , G03F7/20 , G03F7/32
摘要： A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.
摘要翻译：一种方法包括在基底结构之上形成第一光致抗蚀剂层，在基底结构上形成目标特征，在第一光致抗蚀剂层上进行未图案化曝光，以及显影第一光刻胶层。在显影步骤之后，第一光致抗蚀剂层的角部保留在基底结构的顶表面和目标特征的边缘之间的角落处。在目标特征，基底结构和第一光致抗蚀剂层的角部上形成第二光致抗蚀剂层。使用图案化光刻掩模曝光第二光致抗蚀剂层。图案化第二光致抗蚀剂层以形成图案化的光刻胶。

4. 发明授权

US09372406B2 Film portion at wafer edge 有权
标题翻译：晶片边缘处的薄膜部分
公开(公告)号：US09372406B2
公开(公告)日：2016-06-21
申请号：US13764155
申请日：2013-02-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chun-Wei Chang , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： H01L21/311 , G03F7/20 , H01L21/308 , H01L21/027 , G03F7/00 , H01L21/3105
CPC分类号： G03F7/20 , G03F7/0002 , H01L21/0274 , H01L21/3085 , H01L21/31058 , H01L21/31144
摘要： A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer.
摘要翻译：图案化晶片的基板上的薄膜层，以形成膜层的第一多个区域和薄膜层的第二多个区域。去除膜层的第一多个区域。膜层的第二多个区域保持在基板上。膜层的第一部分保持在基板上。膜层的第一部分的第一边缘基本上靠近晶片的边缘。膜层的第一部分限定了晶片的边界。

5. 发明申请

US20150249109A1 METHOD OF FABRICATING A METAL GRID FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的金属网的方法
公开(公告)号：US20150249109A1
公开(公告)日：2015-09-03
申请号：US14194859
申请日：2014-03-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Chien Wang , Chihy-Yuan Cheng , Chuan-Ling Wu , Chun-Chang Chen , Wang-Pen Mo , Feng-Jia Shiu
IPC分类号： H01L27/146
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14645 , H01L27/14689 , H01L27/1469
摘要： A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench.
摘要翻译：提供了一种用于制造图像传感器装置的方法。该方法包括在衬底的背表面上沉积第一介电层，在第一介电层上形成脊，在第一介电层上沉积第二电介质层，包括填充两个相邻脊之间的空间。该方法还包括去除脊以在第二电介质层中形成沟槽并在沟槽中形成金属栅格。

6. 发明授权

US09651869B2 Film portion at wafer edge 有权
公开(公告)号：US09651869B2
公开(公告)日：2017-05-16
申请号：US14680546
申请日：2015-04-07
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chun-Wei Chang , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： G03F7/20 , H01L21/308 , H01L21/027 , G03F7/00 , H01L21/3105 , H01L21/311
CPC分类号： G03F7/20 , G03F7/0002 , H01L21/0274 , H01L21/3085 , H01L21/31058 , H01L21/31144
摘要： A method for preparing a wafer includes forming a film layer on a substrate of the wafer; coating the film layer with a photoresist layer; exposing a first portion of the photoresist layer to a beam of light; and patterning a second portion of the photoresist layer after performing exposing the first portion of the photoresist layer. A cross-link reaction is caused on the first portion of the photoresist layer and the first portion of the photoresist layer is converted to a reacted first portion of the photoresist layer. The reacted first portion of the photoresist layer is near an edge of the wafer. The second portion of the photoresist layer is different from the reacted first portion of the photoresist layer. The second portion of the photoresist layer is converted to a patterned second portion of the photoresist layer.

7. 发明授权

US09349662B2 Test structure placement on a semiconductor wafer 有权
标题翻译：测试结构放置在半导体晶圆上
公开(公告)号：US09349662B2
公开(公告)日：2016-05-24
申请号：US13692414
申请日：2012-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chuan-Ling Wu , Cheng-Hsien Chuang , Chun-Chang Chen , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： H01L21/66
CPC分类号： H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.
摘要翻译：提供一种制造集成电路器件的方法。该方法包括在半导体晶片上形成多个间隔开的集成电路管芯，并在与多个间隔开的集成电路管芯相邻的半导体晶片上形成专用的测试管芯，该专用的测试管芯包括具有第一宽度的测试结构顶视图并可操作以产生晶片评估数据。此外，所述方法包括形成插入在所述多个间隔开的集成电路管芯之间的划线区域，所述划线区域具有由顶视图中的相邻集成电路管芯之间的距离限定的第二宽度，所述第二宽度小于第一宽度和划线区域没有测试结构。

8. 发明授权

US09153620B2 Method of fabricating a metal grid for semiconductor device 有权
标题翻译：制造半导体器件的金属栅格的方法
公开(公告)号：US09153620B2
公开(公告)日：2015-10-06
申请号：US14194859
申请日：2014-03-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Chien Wang , Chihy-Yuan Cheng , Chuan-Ling Wu , Chun-Chang Chen , Wang-Pen Mo , Feng-Jia Shiu
IPC分类号： H01L21/20 , H01L27/146
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14645 , H01L27/14689 , H01L27/1469
摘要： A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench.
摘要翻译：提供了一种用于制造图像传感器装置的方法。该方法包括在衬底的背表面上沉积第一介电层，在第一介电层上形成脊，在第一介电层上沉积第二电介质层，包括填充两个相邻脊之间的空间。该方法还包括去除脊以在第二电介质层中形成沟槽并在沟槽中形成金属栅格。

9. 发明授权

US09875892B2 Method of forming a photoresist layer 有权
公开(公告)号：US09875892B2
公开(公告)日：2018-01-23
申请号：US14707387
申请日：2015-05-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chun-Wei Chang , Chih-Chien Wang , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： B05D3/12 , H01L21/02 , H01L21/027 , H01L21/67 , B05D1/00
CPC分类号： H01L21/02282 , B05D1/005 , G03F7/091 , G03F7/162 , H01L21/0271 , H01L21/0276 , H01L21/6715
摘要： A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.

10. 发明授权

US09791775B2 Lithography process on high topology features 有权
公开(公告)号：US09791775B2
公开(公告)日：2017-10-17
申请号：US15067937
申请日：2016-03-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chun-Wei Chang , Hong-Da Lin , Chih-Chien Wang , Chun-Chang Chen , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： G03F7/207 , G03F7/00 , G03F7/09 , G03F7/16 , G03F7/20 , G03F7/32
CPC分类号： G03F7/0035 , G03F7/091 , G03F7/16 , G03F7/20 , G03F7/32
摘要： A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

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