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1. 发明授权

US11378894B2 Lithography system with an embedded cleaning module 有权
公开(公告)号：US11378894B2
公开(公告)日：2022-07-05
申请号：US16665585
申请日：2019-10-28
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shang-Chieh Chien , Jeng-Horng Chen , Jui-Ching Wu , Chia-Chen Chen , Hung-Chang Hsieh , Chi-Lun Lu , Chia-Hao Yu , Shih-Ming Chang , Anthony Yen
IPC分类号： G03F7/20
摘要： The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.

2. 发明授权

US11081394B2 Method of making a FinFET device 有权
公开(公告)号：US11081394B2
公开(公告)日：2021-08-03
申请号：US16153956
申请日：2018-10-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Wen-Hung Tseng , Tzung-Hua Lin , Hung-Chang Hsieh
IPC分类号： H01L21/8234 , H01L21/308 , H01L21/311 , H01L21/762 , H01L27/088
摘要： A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

3. 发明申请

US20200286782A1 Method of Semiconductor Integrated Circuit Fabrication 审中-公开
公开(公告)号：US20200286782A1
公开(公告)日：2020-09-10
申请号：US16880718
申请日：2020-05-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Hung-Chang Hsieh , Wen-Hung Tseng
IPC分类号： H01L21/768 , H01L29/417 , H01L21/28 , H01L29/423 , H01L21/8238 , H01L29/43 , H01L27/092 , H01L21/8234 , H01L29/49 , H01L29/51 , H01L21/321 , H01L23/532 , H01L23/528 , H01L23/522 , H01L23/485
摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

4. 发明授权

US10672656B2 Method of semiconductor integrated circuit fabrication 审中-公开
公开(公告)号：US10672656B2
公开(公告)日：2020-06-02
申请号：US14875535
申请日：2015-10-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Hung-Chang Hsieh , Wen-Hung Tseng
IPC分类号： H01L21/768 , H01L29/417 , H01L21/28 , H01L29/423 , H01L21/8238 , H01L21/8234 , H01L29/49 , H01L29/43 , H01L27/092 , H01L29/51 , H01L21/321 , H01L23/532 , H01L23/528 , H01L23/522 , H01L23/485 , H01L21/4763 , H01L21/3105 , H01L29/66
摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

5. 发明授权

US09805154B2 Method of lithography process with inserting scattering bars 有权
公开(公告)号：US09805154B2
公开(公告)日：2017-10-31
申请号：US14713360
申请日：2015-05-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Irene Ho , Ai-Jen Hung , Hung-Chang Hsieh , Kuei-Liang Lu , Ya Hui Chang
IPC分类号： G06F17/50 , G03F1/00 , G03F7/00 , G03F1/36 , G03F7/20
CPC分类号： G06F17/5072 , G03F1/144 , G03F1/36 , G03F7/70433 , G03F7/70441 , G06F17/5081
摘要： The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.

6. 发明授权

US09651869B2 Film portion at wafer edge 有权
公开(公告)号：US09651869B2
公开(公告)日：2017-05-16
申请号：US14680546
申请日：2015-04-07
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chun-Wei Chang , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： G03F7/20 , H01L21/308 , H01L21/027 , G03F7/00 , H01L21/3105 , H01L21/311
CPC分类号： G03F7/20 , G03F7/0002 , H01L21/0274 , H01L21/3085 , H01L21/31058 , H01L21/31144
摘要： A method for preparing a wafer includes forming a film layer on a substrate of the wafer; coating the film layer with a photoresist layer; exposing a first portion of the photoresist layer to a beam of light; and patterning a second portion of the photoresist layer after performing exposing the first portion of the photoresist layer. A cross-link reaction is caused on the first portion of the photoresist layer and the first portion of the photoresist layer is converted to a reacted first portion of the photoresist layer. The reacted first portion of the photoresist layer is near an edge of the wafer. The second portion of the photoresist layer is different from the reacted first portion of the photoresist layer. The second portion of the photoresist layer is converted to a patterned second portion of the photoresist layer.

7. 发明授权

US09466486B2 Method for integrated circuit patterning 有权
标题翻译：集成电路图案化方法
公开(公告)号：US09466486B2
公开(公告)日：2016-10-11
申请号：US14014771
申请日：2013-08-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Feng Shieh , Ru-Gun Liu , Hung-Chang Hsieh , Tien-I Bao , Chung-Ju Lee , Shau-Lin Shue
IPC分类号： H01L21/308 , H01L21/311 , G03F7/26 , H01L21/033 , H01L21/768 , H01L29/66
CPC分类号： H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/76816 , H01L29/66795
摘要： A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate.
摘要翻译：形成目标图案的方法包括：在切割掩模的基板中形成第一沟槽; 用第一主掩模在衬底上形成第一多条线，其中第一主掩模包括与第一沟槽重叠的至少一条线，由此由第一沟槽切割成至少两条线; 在所述基板上形成间隔层，并且在所述第一多条线路中的所述第一多条线路和所述侧壁上形成间隔层; 通过第二主掩模在间隔层上形成图案化材料层，由此图案化材料层和间隔层共同限定第二多个沟槽; 去除所述间隔层的至少一部分以暴露所述第一多条线; 并且去除第一多个线，从而在衬底上形成图案化间隔层。

8. 发明授权

US09349662B2 Test structure placement on a semiconductor wafer 有权
标题翻译：测试结构放置在半导体晶圆上
公开(公告)号：US09349662B2
公开(公告)日：2016-05-24
申请号：US13692414
申请日：2012-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chuan-Ling Wu , Cheng-Hsien Chuang , Chun-Chang Chen , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： H01L21/66
CPC分类号： H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.
摘要翻译：提供一种制造集成电路器件的方法。该方法包括在半导体晶片上形成多个间隔开的集成电路管芯，并在与多个间隔开的集成电路管芯相邻的半导体晶片上形成专用的测试管芯，该专用的测试管芯包括具有第一宽度的测试结构顶视图并可操作以产生晶片评估数据。此外，所述方法包括形成插入在所述多个间隔开的集成电路管芯之间的划线区域，所述划线区域具有由顶视图中的相邻集成电路管芯之间的距离限定的第二宽度，所述第二宽度小于第一宽度和划线区域没有测试结构。

9. 发明申请

US20160118303A1 Method of Forming Source/Drain Contact 有权
标题翻译：形成源/漏接触的方法
公开(公告)号：US20160118303A1
公开(公告)日：2016-04-28
申请号：US14521965
申请日：2014-10-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Jhih Kuo , Yu-Hsien Lin , Hung-Chang Hsieh , Jhun Hua Chen
IPC分类号： H01L21/8234 , H01L29/49 , H01L21/311 , H01L29/51 , H01L27/088 , H01L29/66
CPC分类号： H01L21/823475 , H01L21/76829 , H01L21/76895 , H01L21/76897 , H01L21/823468 , H01L27/088 , H01L29/165 , H01L29/517 , H01L29/6656 , H01L29/66636
摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.
摘要翻译：公开了制造半导体器件的方法。该方法包括在衬底上形成栅极结构。栅极结构包括第一硬掩模层。该方法还包括在与栅极结构相邻的衬底中形成源极/漏极（S / D）特征，在栅极结构的侧壁上形成侧壁间隔物。侧壁间隔件在其上部具有背离门结构的外边缘。该方法还包括沿着栅极结构的侧壁并沿着侧壁间隔物的外边缘形成第二间隔物，在栅极结构上方形成电介质层，形成延伸穿过电介质层的沟槽以暴露源/漏特征，而栅极结构被第一硬掩模层和具有第二间隔物的侧壁间隔物保护。该方法还包括在沟槽中形成接触特征。

10. 发明授权

US09158884B2 Method and system for repairing wafer defects 有权
标题翻译：修复晶圆缺陷的方法和系统
公开(公告)号：US09158884B2
公开(公告)日：2015-10-13
申请号：US14071352
申请日：2013-11-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shih-Ming Chang , Chih-Ming Lai , Hung-Chang Hsieh
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/72 , G03F7/7065 , G06F2217/06 , G06F2217/12
摘要： A method of lithographic defect detection and repair is disclosed. In an exemplary embodiment, the method of patterning a workpiece comprises receiving a mask for patterning a workpiece. The mask is inspected for defects, and a mask defect is identified that is repairable in the workpiece. The workpiece is lithographically exposed using the mask, and a defect is repaired within the workpiece based on the identified mask defect. The method can further comprise comparing defects across the workpiece to determine repeating defects and determining a spacing between the repeating defects. A distance between a first focal point and a second focal point of a lithographic system can be configured to correspond to the spacing between the repeating defects. Thus, a first repeating defect and a second repeating defect can be repaired concurrently.
摘要翻译：公开了一种光刻缺陷检测和修复方法。在示例性实施例中，图案化工件的方法包括接收用于图案化工件的掩模。对掩模进行缺陷检查，并识别出可在工件中修复的掩模缺陷。使用掩模将工件光刻曝光，并且基于所识别的掩模缺陷在工件内修复缺陷。该方法还可以包括比较穿过工件的缺陷以确定重复缺陷并确定重复缺陷之间的间距。光刻系统的第一焦点和第二焦点之间的距离可被配置为对应于重复缺陷之间的间隔。因此，可以同时修复第一重复缺陷和第二重复缺陷。

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