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1. 发明申请

US20230013600A1 Circuits and Methods for a Cascade Phase Locked Loop 有权
公开(公告)号：US20230013600A1
公开(公告)日：2023-01-19
申请号：US17572703
申请日：2022-01-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ruey-Bin Sheen
IPC分类号： H03L7/099 , H03L7/081
摘要： Systems and methods are provided for a cascade phase locked loop. A first phase locked loop receives a reference clock signal having a first frequency and generates a high frequency clock signal that is phase aligned with the reference clock signal. A first divider divides the high frequency clock signal to generate a middle frequency clock signal, and a second divider divides the middle frequency clock signal to generate a low frequency reference clock signal. A second phase locked loop receives the low frequency reference clock signal and generates an output signal, compares the output signal to the low frequency reference clock signal to generate a frequency increasing (UP) signal that indicates a phase difference between the output signal and the low frequency reference clock signal. A delay locked loop receives the middle frequency clock signal and the frequency increasing (UP) signal and delays the middle frequency clock signal based on the frequency increasing (UP) signal to generate the realignment clock signal. The second phase lock loop receives the realignment clock signal and adjusts the phase difference between the output signal and the low frequency reference clock signal based on the realignment clock signal.

2. 发明申请

US20230008340A1 Coarse-Mover with Sequential Finer Tuning Step 有权
公开(公告)号：US20230008340A1
公开(公告)日：2023-01-12
申请号：US17572690
申请日：2022-01-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Jason Hsu , Ruey-Bin Sheen
IPC分类号： H03L7/099 , H03L7/187
摘要： A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.

3. 发明授权

US11211936B1 Delay lock loop circuits and methods for operating same 有权
公开(公告)号：US11211936B1
公开(公告)日：2021-12-28
申请号：US17141276
申请日：2021-01-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ya-Tin Chang , Ruey-Bin Sheen , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： H03L7/081 , H03L7/095
摘要： Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

4. 发明申请

US20210270879A1 Systems and Methods for Duty Cycle Measurement 有权
公开(公告)号：US20210270879A1
公开(公告)日：2021-09-02
申请号：US17124580
申请日：2020-12-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ruey-Bin Sheen , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： G01R29/02 , H03K19/21 , H03K3/037 , H03K5/00 , G01R25/00
摘要： Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

5. 发明授权

US11595050B2 Circuits and methods for a cascade phase locked loop 有权
公开(公告)号：US11595050B2
公开(公告)日：2023-02-28
申请号：US17572703
申请日：2022-01-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ruey-Bin Sheen
IPC分类号： H03L7/099 , H03L7/081
摘要： Systems and methods are provided for a cascade phase locked loop. A first phase locked loop receives a reference clock signal having a first frequency and generates a high frequency clock signal that is phase aligned with the reference clock signal. A first divider divides the high frequency clock signal to generate a middle frequency clock signal, and a second divider divides the middle frequency clock signal to generate a low frequency reference clock signal. A second phase locked loop receives the low frequency reference clock signal and generates an output signal, compares the output signal to the low frequency reference clock signal to generate a frequency increasing (UP) signal that indicates a phase difference between the output signal and the low frequency reference clock signal. A delay locked loop receives the middle frequency clock signal and the frequency increasing (UP) signal and delays the middle frequency clock signal based on the frequency increasing (UP) signal to generate the realignment clock signal. The second phase lock loop receives the realignment clock signal and adjusts the phase difference between the output signal and the low frequency reference clock signal based on the realignment clock signal.

6. 发明申请

US20230016886A1 Delay Lock Loop Circuits and Methods for Operating Same 有权
公开(公告)号：US20230016886A1
公开(公告)日：2023-01-19
申请号：US17955615
申请日：2022-09-29
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ya-Tin Chang , Ruey-Bin Sheen , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： H03L7/081 , H03L7/095
摘要： Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

7. 发明授权

US11545983B2 Systems and methods for phase locked loop realignment with skew cancellation 有权
公开(公告)号：US11545983B2
公开(公告)日：2023-01-03
申请号：US17159335
申请日：2021-01-27
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ruey-Bin Sheen , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： H03L7/089 , H03D13/00 , H03L7/099 , H03L7/093
摘要： Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

8. 发明申请

US20220407527A1 Programmable Regulator Voltage Controlled Ring Oscillator 有权
公开(公告)号：US20220407527A1
公开(公告)日：2022-12-22
申请号：US17865464
申请日：2022-07-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ruey-Bin Sheen , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： H03L7/099 , H03K3/03 , H03K3/013
摘要： Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

9. 发明授权

US11424751B1 Programmable regulator voltage controlled ring oscillator 有权
公开(公告)号：US11424751B1
公开(公告)日：2022-08-23
申请号：US17349991
申请日：2021-06-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ruey-Bin Sheen , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： H03L7/099 , H03K3/013 , H03K3/03
摘要： Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

10. 发明授权

US09621171B1 Frequency scaling method, circuit and associated all-digital phase-locked loop 有权
公开(公告)号：US09621171B1
公开(公告)日：2017-04-11
申请号：US14871602
申请日：2015-09-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Tsung-Hsien Tsai , Chih-Hsien Chang
IPC分类号： H03L7/095 , H03L7/099 , H03L7/10 , H03K7/06 , H03L7/091 , H03L7/093
CPC分类号： H03L7/0994 , H03K7/06 , H03L2207/50
摘要： A frequency scaling method is disclosed. The method is used for changing an output frequency of an all-digital phase-locked loop (ADPLL) from a first frequency to a second frequency different from the first frequency. The method includes: stopping a feeding of a first oscillator tuning word (OTW) to a digitally controlled oscillator (DCO) of the ADPLL, wherein the first OTW is generated based on a phase detecting result obtained with respect to the first frequency; feeding a second OTW to the DCO in order to change the output frequency from the first frequency to the second frequency; and performing a zero phase restart (ZPR) operation to produce the phase detecting result according to the second frequency. An associated ADPLL and a frequency scaling circuit are also disclosed.

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