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1. 发明申请

US20180183423A1 System and Method for Anti-Ambipolar Heterojunctions from Solution-Processed Semiconductors 审中-公开
公开(公告)号：US20180183423A1
公开(公告)日：2018-06-28
申请号：US15897739
申请日：2018-02-15
申请人： Northwestern University
发明人： Deep M. Jariwala , Vinod K. Sangwan , Weichao Xu , Hyungil Kim , Tobin J. Marks , Mark C. Hersam
IPC分类号： H03K7/06 , H01L51/00 , H01L51/05 , H01L51/10
CPC分类号： H03K7/06 , H01L27/283 , H01L27/286 , H01L29/78693 , H01L51/0003 , H01L51/0017 , H01L51/0048 , H01L51/0545 , H01L51/0562 , H01L51/105 , H01L2251/303
摘要： Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.

2. 发明授权

US09940303B2 Method and apparatus for decimation in frequency FFT butterfly 有权
公开(公告)号：US09940303B2
公开(公告)日：2018-04-10
申请号：US15060475
申请日：2016-03-03
申请人： Tempo Semiconductor, Inc.
发明人： Darrell Eugene Tinker
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , G06F1/025 , H02M2001/0003 , H03K7/02 , H03K7/06 , H03K7/08 , H03K7/10 , H03K17/165
摘要： A pipelined decimation in frequency FFT butterfly method, and an apparatus to perform this method comprising: a data memory with at least one read port and one write port; an add/subtract unit receiving data from the memory; a multiply/accumulate unit receiving data from the add/subtract unit; a source of coefficients, from logic gates or a coefficient memory, to supply FFT twiddle factors to the multiply/accumulate unit; a shifter receiving data from at least one of the add/subtract unit and the multiply/accumulate unit, the shifter supplying data to the write port of the data memory; wherein the apparatus performs these calculations in four cycles of the add/subtract unit and in four cycles of the multiply/accumulate unit, using complex arithmetic.

3. 发明授权

US09698673B2 Method for controlling an electronic circuit 有权
公开(公告)号：US09698673B2
公开(公告)日：2017-07-04
申请号：US14916233
申请日：2014-09-05
申请人： Commissariat è l'Energie Atomique et aux Energies Alternatives , Université de Montpellier
发明人： Yeter Akgul , Edith Beigne , Pascal Benoit , Suzanne Lesecq , Diego Puschini Pascual
IPC分类号： H02M3/04 , G06F1/32 , H03K7/06
CPC分类号： H02M3/04 , G06F1/324 , H03K7/06 , Y02D10/126
摘要： A method for controlling an electronic circuit by means of the first, second and third operating parameters, comprises: determining a range of variation of the third parameter for each value of the first parameter by varying the second parameter, said ranges being different; determining a target value of the third parameter; if the target value is within one of the ranges, operating the electronic circuit by setting the third parameter to the target value; and in the opposite case, selecting the two ranges framing the target value and operating the electronic circuit by consecutively bringing the third parameter into each one of the selected ranges.

4. 发明申请

US20170187366A1 DOUBLE FREQUENCY-SHIFT KEYING MODULATING DEVICE 有权
公开(公告)号：US20170187366A1
公开(公告)日：2017-06-29
申请号：US15242539
申请日：2016-08-21
申请人： National Chi Nan University
发明人： Yo-Sheng LIN , Chien-Chu CHI , Ching-Hung PENG
IPC分类号： H03K7/06 , H02M3/07 , H03L7/18 , H03B5/12
CPC分类号： H03K7/06 , H02M3/07 , H03B5/1212 , H03B5/1228 , H03B5/1246 , H03B19/12 , H03C3/20 , H03L7/099 , H03L7/18
摘要： A double frequency-shift keying modulating device includes a modulation module. The modulation module receives an oscillating signal and a digital signal, and generates a modulation output signal that has a first frequency. The first frequency is associated with a frequency of the oscillating signal and varies periodically at a second frequency. The second frequency is associated with the digital signal and the frequency of the oscillating signal.

5. 发明授权

US09621146B2 Digital current equalization method and power supply module 有权
公开(公告)号：US09621146B2
公开(公告)日：2017-04-11
申请号：US14586109
申请日：2014-12-30
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Xiaodong Fan
IPC分类号： G05F1/00 , H03K7/06 , H02M3/158
CPC分类号： H03K7/06 , H02M3/1584
摘要： A digital current equalization method includes: acquiring a current value from a counter preset value loading module in each synchronization period; generating a continuous variable frequency pulse according to the current value, and receiving a synchronization signal transmitted by a phase inverter connected to the PFM generator; transmitting, according to the synchronization signal, the continuous variable frequency pulse to the digital current equalization bus through an OC gate of a triode connected to the PFM generator; counting a frequency of the continuous variable frequency pulse on the digital current equalization bus, where an acquired frequency count value is used to represent a current magnitude of a power supply module, which currently outputs a greatest current, of the foregoing power supply module and a power supply module connected in parallel with the foregoing power supply module to accordingly adjust the output current of the foregoing power supply module.

6. 发明申请

US20160285444A1 CURRENT TO FREQUENCY CONVERTER 有权
标题翻译：当前频率转换器
公开(公告)号：US20160285444A1
公开(公告)日：2016-09-29
申请号：US14670628
申请日：2015-03-27
申请人： RAYTHEON COMPANY
发明人： Martin S. Denham , Bruce E. Bozovich
IPC分类号： H03K7/06 , H04N5/3745
CPC分类号： H03K7/06 , H04N5/357 , H04N5/37455
摘要： According to one aspect, embodiments herein provide a current to frequency converter comprising a node configured to be coupled to a photodetector and to receive a photo-current from the photodetector, a capacitor having a first terminal and a second terminal and configured to accumulate electrical charge derived from the photo-current on the first terminal and the second terminal, a switch network configured to selectively couple one of the first terminal and the second terminal to the node, and a Master-Slave (MS) Flip Flop (FF) coupled to the switch network and configured to operate the switch network to toggle which of the first terminal and the second terminal is coupled to the node based on a voltage at the node.
摘要翻译：根据一个方面，本文的实施例提供了一种电流到频率转换器，其包括被配置为耦合到光电检测器并且从光电检测器接收光电流的节点，具有第一端子和第二端子并且被配置为累积电荷源自第一终端和第二终端上的光电流的开关网络，被配置为选择性地将第一终端和第二终端中的一个耦合到节点的开关网络以及耦合到第一终端和第二终端的主从触发器（FF）所述交换机网络并且被配置为操作所述交换机网络，以基于所述节点处的电压来切换所述第一终端和所述第二终端中的哪一个耦合到所述节点。

7. 发明申请

US20160182031A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20160182031A1
公开(公告)日：2016-06-23
申请号：US14689433
申请日：2015-04-17
申请人： SK hynix Inc.
发明人： Choung Ki SONG
IPC分类号： H03K7/06
CPC分类号： H03K7/06 , H03K5/00006 , H03K5/135
摘要： A semiconductor apparatus includes a multiplication control block configured to generate a plurality of frequency control signals according to an input clock and a multiplication determination signal; and a clock output block configured to generate an output clock according to the input clock, the multiplication determination signal and the plurality of frequency control signals.
摘要翻译：一种半导体装置，包括乘法控制块，被配置为根据输入时钟和乘法确定信号产生多个频率控制信号; 以及时钟输出块，被配置为根据输入时钟，乘法确定信号和多个频率控制信号产生输出时钟。

8. 发明申请

US20160111061A1 LOW POWER HIGH FREQUENCY DIGITAL PULSE FREQUENCY MODULATOR 有权
标题翻译：低功率高频数字脉冲频率调制器
公开(公告)号：US20160111061A1
公开(公告)日：2016-04-21
申请号：US14129269
申请日：2013-06-10
申请人： Fenardi THENUS , Peng ZOU , Raghu Nandan CHEPURI , Henry K. KOERTZEN
发明人： Fenardi THENUS , Peng ZOU , Raghu Nandan CHEPURI , Henry K. KOERTZEN
IPC分类号： G09G5/00 , H03K17/284 , G06F3/041 , H03K7/06 , H02M3/158 , H03K5/14 , H03K7/08
CPC分类号： G09G5/006 , G06F3/0412 , G09G2330/021 , H02M3/158 , H02M3/1584 , H02M2001/0009 , H02M2001/0032 , H02M2003/1586 , H03K5/14 , H03K7/06 , H03K7/08 , H03K17/284 , Y02B70/16
摘要： Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch.
摘要翻译：描述了一种装置，包括：可编程延迟线（PDL），用于接收作为输入的脉宽调制（PWM）信号并产生第一输出; 选择单元，其可操作以提供PWM信号或其反相版本作为第二输出; 以及连接到PDL的顺序单元，该顺序单元用第一输出对第二输出进行采样，该顺序单元用于产生脉冲 - 频率调制（PFM）输出。还描述了一种电压调节器，其包括：用于耦合到负载的相互耦合的片上电感器; 耦合到相互耦合的片上电感器的桥，包括低侧开关和高侧开关; PWM控制器，用于在第一负载电流期间控制所述低侧和高侧开关; 以及PFM控制器，用于在第二负载电流期间控制低侧和高侧开关，所述第二负载电流小于所述第一负载电流，所述PFM控制器包括：比较器，用于将所述负载的输出电压与参考电压; 以及耦合到比较器的用于确定高侧开关的导通持续时间的第一PDL。

9. 发明授权

US09299408B2 Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid 有权
标题翻译：集成电路，包括在数据信号有效时改变时钟信号频率的电路
公开(公告)号：US09299408B2
公开(公告)日：2016-03-29
申请号：US14050107
申请日：2013-10-09
申请人： Rambus Inc.
发明人： Brian Hing-Kit Tsang , Jared L. Zerbe
IPC分类号： G11C11/16 , G11C8/18 , H03L7/00 , G11C7/10 , G11C7/22 , H01L43/08 , G11C11/15
CPC分类号： H03K5/133 , G06F13/1689 , G11C7/10 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/15 , G11C11/16 , H01L43/08 , H03K3/0315 , H03K7/06 , H03K2005/00019 , H03L7/00 , Y02D10/14
摘要： Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
摘要翻译：描述用于传达信息的方法和装置。在一些实施例中，第一集成电路（IC）向第二IC提供时钟信号和数据信号，其中数据信号的数据位根据时钟信号定时，并且其中时钟信号的频率能够甚至当数据信号有效时也被改变。

10. 发明申请

US20150180332A1 DIGITAL CURRENT EQUALIZATION METHOD AND POWER SUPPLY MODULE 有权
标题翻译：数字电流均衡方法和电源模块
公开(公告)号：US20150180332A1
公开(公告)日：2015-06-25
申请号：US14586109
申请日：2014-12-30
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Xiaodong FAN
IPC分类号： H02M3/04 , H03K7/06
CPC分类号： H03K7/06 , H02M3/1584
摘要： A digital current equalization method includes: acquiring a current value from a counter preset value loading module in each synchronization period; generating a continuous variable frequency pulse according to the current value, and receiving a synchronization signal transmitted by a phase inverter connected to the PFM generator; transmitting, according to the synchronization signal, the continuous variable frequency pulse to the digital current equalization bus through an OC gate of a triode connected to the PFM generator; counting a frequency of the continuous variable frequency pulse on the digital current equalization bus, where an acquired frequency count value is used to represent a current magnitude of a power supply module, which currently outputs a greatest current, of the foregoing power supply module and a power supply module connected in parallel with the foregoing power supply module to accordingly adjust the output current of the foregoing power supply module.
摘要翻译：数字电流均衡方法包括：在每个同步周期内从计数器预置值加载模块获取当前值; 根据当前值产生连续可变频率脉冲，并接收由连接到PFM发生器的相位逆变器发送的同步信号; 根据同步信号，通过连接到PFM发生器的三极管的OC门将连续可变频率脉冲发送到数字电流均衡总线; 对数字电流均衡总线上的连续可变频率脉冲的频率进行计数，其中采集的频率计数值用于表示当前输出最大电流的上述电源模块的电源模块的电流幅度，以及电源模块与上述电源模块并联连接，以相应地调节前述电源模块的输出电流。

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