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1. 发明申请

US20080206901A1 PULSED-PLASMA SYSTEM WITH PULSED REACTION GAS REPLENISH FOR ETCHING SEMICONDUCTOR STRUCTURES 有权
标题翻译：具有脉冲反应气体的脉冲等离子体系统用于蚀刻半导体结构
公开(公告)号：US20080206901A1
公开(公告)日：2008-08-28
申请号：US11678047
申请日：2007-02-22
申请人： TAE WON KIM , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorow , Shashank C. Deshmukh
发明人： TAE WON KIM , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorow , Shashank C. Deshmukh
IPC分类号： H01L21/3065
CPC分类号： H01L21/32137 , H01L21/3065 , H01L21/31116
摘要： A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.
摘要翻译：描述了一种具有脉冲反应气体的脉冲等离子体系统，用于蚀刻半导体结构。在一个实施例中，通过施加脉冲等离子体蚀刻工艺去除一部分样品。脉冲等离子体蚀刻工艺包括多个占空比，其中每个占空比表示等离子体的导通状态和断开状态的组合。等离子体由反应气体产生，其中反应气体在等离子体的关闭状态期间补充，而不是在ON状态下补充。在另一个实施例中，通过施加连续的等离子体蚀刻工艺来移除样品的第一部分。然后连续等离子体蚀刻工艺终止，通过施加具有脉冲反应气体补充的脉冲等离子体蚀刻工艺来除去样品的第二部分。

2. 发明申请

US20080206900A1 PULSED-PLASMA SYSTEM FOR ETCHING SEMICONDUCTOR STRUCTURES 有权
标题翻译：用于蚀刻半导体结构的脉冲等离子体系统
公开(公告)号：US20080206900A1
公开(公告)日：2008-08-28
申请号：US11678041
申请日：2007-02-22
申请人： TAE WON KIM , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorow , Shashank C. Deshmukh
发明人： TAE WON KIM , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorow , Shashank C. Deshmukh
IPC分类号： H01L21/3065
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/31122 , H01L21/67069
摘要： A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
摘要翻译：描述了用于蚀刻半导体结构的脉冲等离子体系统。在一个实施例中，通过施加脉冲等离子体处理来去除样品的一部分，其中脉冲等离子体处理包括多个占空比。占空比的导通状态具有足够短的持续时间，从而基本上抑制了与样品相邻的反应区域中的微负荷，同时占空比的关闭状态持续足够长，从而基本上能够去除一组蚀刻来自反应区域的副产物。在另一个实施方案中，通过施加连续的等离子体工艺来除去样品的第一部分。然后连续等离子体处理被终止，并且通过施加脉冲等离子体工艺来除去样品的第二部分。

3. 发明授权

US07737042B2 Pulsed-plasma system for etching semiconductor structures 有权
标题翻译：用于蚀刻半导体结构的脉冲等离子体系统
公开(公告)号：US07737042B2
公开(公告)日：2010-06-15
申请号：US11678041
申请日：2007-02-22
申请人： Tae Won Kim , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorow , Shashank C. Deshmukh
发明人： Tae Won Kim , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorow , Shashank C. Deshmukh
IPC分类号： H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/31122 , H01L21/67069
摘要： A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
摘要翻译：描述了用于蚀刻半导体结构的脉冲等离子体系统。在一个实施例中，通过施加脉冲等离子体处理来去除样品的一部分，其中脉冲等离子体处理包括多个占空比。占空比的导通状态具有足够短的持续时间，从而基本上抑制了与样品相邻的反应区域中的微负荷，同时占空比的关闭状态持续足够长，从而基本上能够去除一组蚀刻来自反应区域的副产物。在另一个实施方案中，通过施加连续的等离子体工艺来除去样品的第一部分。然后连续等离子体处理被终止，并且通过施加脉冲等离子体工艺来除去样品的第二部分。

4. 发明授权

US07771606B2 Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures 有权
标题翻译：具有脉冲反应气体的脉冲等离子体系统补充用于蚀刻半导体结构
公开(公告)号：US07771606B2
公开(公告)日：2010-08-10
申请号：US11678047
申请日：2007-02-22
申请人： Tae Won Kim , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorow , Shashank C. Deshmukh
发明人： Tae Won Kim , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorow , Shashank C. Deshmukh
IPC分类号： B44C1/22 , C03C25/68 , C03C15/00 , C23F1/00
CPC分类号： H01L21/32137 , H01L21/3065 , H01L21/31116
摘要： A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.
摘要翻译：描述了一种具有脉冲反应气体的脉冲等离子体系统，用于蚀刻半导体结构。在一个实施例中，通过施加脉冲等离子体蚀刻工艺去除一部分样品。脉冲等离子体蚀刻工艺包括多个占空比，其中每个占空比表示等离子体的导通状态和断开状态的组合。等离子体由反应气体产生，其中反应气体在等离子体的关闭状态期间补充，而不是在ON状态下补充。在另一个实施例中，通过施加连续的等离子体蚀刻工艺来移除样品的第一部分。然后连续等离子体蚀刻工艺终止，通过施加具有脉冲反应气体补充的脉冲等离子体蚀刻工艺来除去样品的第二部分。

5. 发明授权

US07718538B2 Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates 有权
标题翻译：具有用于蚀刻半导体衬底的脉冲样品偏置的脉冲等离子体系统
公开(公告)号：US07718538B2
公开(公告)日：2010-05-18
申请号：US11677472
申请日：2007-02-21
申请人： Tae Won Kim , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorov , Shashank C. Deshmukh
发明人： Tae Won Kim , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorov , Shashank C. Deshmukh
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , C23F4/00 , H01J37/32009 , H01L21/3065 , H01L21/32137
摘要： A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
摘要翻译：描述了具有用于蚀刻半导体结构的脉冲样本偏置的脉冲等离子体系统。在一个实施例中，通过施加脉冲等离子体处理来去除样品的一部分，其中脉冲等离子体处理包括多个占空比。在每个占空比的导通状态期间，向样品施加负偏压，而在每个占空比的OFF状态期间，零样本被施加到样品。在另一个实施方案中，通过施加连续的等离子体工艺来除去样品的第一部分。然后连续等离子体处理被终止，并且通过施加脉冲等离子体工艺来除去样品的第二部分。

6. 发明申请

US20080197110A1 PULSED-PLASMA SYSTEM WITH PULSED SAMPLE BIAS FOR ETCHING SEMICONDUCTOR SUBSTRATES 有权
标题翻译：具有用于蚀刻半导体衬底的脉冲样品偏置的脉冲等离子体系统
公开(公告)号：US20080197110A1
公开(公告)日：2008-08-21
申请号：US11677472
申请日：2007-02-21
申请人： Tae Won Kim , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorov , Shashank C. Deshmukh
发明人： Tae Won Kim , Kyeong-Tae Lee , Alexander Paterson , Valentin N. Todorov , Shashank C. Deshmukh
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01L21/31116 , C23F4/00 , H01J37/32009 , H01L21/3065 , H01L21/32137
摘要： A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
摘要翻译：描述了具有用于蚀刻半导体结构的脉冲样本偏置的脉冲等离子体系统。在一个实施例中，通过施加脉冲等离子体处理来去除样品的一部分，其中脉冲等离子体处理包括多个占空比。在每个占空比的导通状态期间，向样品施加负偏压，而在每个占空比的OFF状态期间，零样本被施加到样品。在另一个实施方案中，通过施加连续的等离子体工艺来除去样品的第一部分。然后连续等离子体处理被终止，并且通过施加脉冲等离子体工艺来除去样品的第二部分。

7. 发明授权

US07754610B2 Process for etching tungsten silicide overlying polysilicon particularly in a flash memory 失效
标题翻译：用于蚀刻覆盖多晶硅的硅化钨的工艺，特别是在闪速存储器中
公开(公告)号：US07754610B2
公开(公告)日：2010-07-13
申请号：US11445709
申请日：2006-06-02
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/32136 , H01L21/28273 , H01L21/32137
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF3和Cl2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。可以添加SiCl 4以获得额外的选择性。

8. 发明申请

US20070281479A1 Process including silo-chloro passivation for etching tungsten silicide overlying polysilicon 审中-公开
标题翻译：包括用于蚀刻硅化钨覆盖多晶硅的硅 - 氯钝化的方法
公开(公告)号：US20070281479A1
公开(公告)日：2007-12-06
申请号：US11513455
申请日：2006-08-31
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank C. Deshmukh , Meihua Shen , Thorsten B. Lill , Jae Bum Yu
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/32137 , H01L29/40114
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 as an example of a silicon and chlorine containing passivating gas may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF 3和Cl 2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。作为含硅和氯的钝化气体的实例，可以加入作为另外选择性的SiCl 4 Si 3。

9. 发明授权

US5851926A Method for etching transistor gates using a hardmask 失效
标题翻译：使用硬掩模蚀刻晶体管栅极的方法
公开(公告)号：US5851926A
公开(公告)日：1998-12-22
申请号：US724383
申请日：1996-10-01
申请人： Ajay Kumar , Jeffrey Chinn , Shashank C. Deshmukh , Weinan Jiang , Rolf Adolf Guenther , Bruce Minaee , Mark Wiltse
发明人： Ajay Kumar , Jeffrey Chinn , Shashank C. Deshmukh , Weinan Jiang , Rolf Adolf Guenther , Bruce Minaee , Mark Wiltse
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L29/78
CPC分类号： H01L21/32135
摘要： An etchant composition of nitrogen trifluoride and chlorine, preferably also including a passivation material such as hydrogen bromide, etches tungsten silicide-polysilicon gate layers with high selectivity to a thin underlying silicon oxide gate oxide layer to form straight wall, perpendicular profiles with low microloading and excellent profile control.
摘要翻译：三氟化氮和氯的蚀刻剂组合物，优选还包括钝化材料如溴化氢，蚀刻钨硅化物 - 多晶硅栅极层，其具有对薄的底层氧化硅栅极氧化物层的高选择性，以形成具有低微载荷的直壁，垂直剖面，优秀的档案控制。

10. 发明授权

US06924088B2 Method and system for realtime CD microloading control 有权
标题翻译：实时CD微控制方法与系统
公开(公告)号：US06924088B2
公开(公告)日：2005-08-02
申请号：US10464479
申请日：2003-06-18
申请人： David S. L. Mui , Wei Liu , Shashank C. Deshmukh , Hiroki Sasano
发明人： David S. L. Mui , Wei Liu , Shashank C. Deshmukh , Hiroki Sasano
IPC分类号： G03F7/20 , H01L21/66 , G01B11/02
CPC分类号： G03F7/70625 , H01L22/20 , Y10S977/854
摘要： A method and apparatus for processing a semiconductor wafer is provided for reducing CD microloading variation. OCD metrology is used to inspect a wafer to determine pre-etch CD microloading, by measuring the CD of dense and isolated photoresist lines. Other parameters can also be measured or otherwise determined, such as sidewall profile, photoresist layer thickness, underlying layer thickness, photoresist pattern density, open area, etc. The inspection results are fed forward to the etcher to determine process parameters, such as resist trim time and/or etch conditions, thereby achieving the desired post-etch CD microloading. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.
摘要翻译：提供了一种用于处理半导体晶片的方法和设备，用于减少CD微型负载变化。 OCD测量用于通过测量致密和隔离的光致抗蚀剂线的CD来检查晶片以确定预蚀刻CD微载入。也可以测量或确定其它参数，例如侧壁轮廓，光致抗蚀剂层厚度，下层厚度，光致抗蚀剂图案密度，开放面积等。检查结果向前馈送到蚀刻器以确定工艺参数，例如抗蚀剂修整时间和/或蚀刻条件，从而实现所需的后蚀刻CD微加载。在某些实施例中，CD和轮廓测量，修剪，蚀刻处理和蚀刻后清洁在受控环境中的单个模块执行。模块执行的所有转移和处理步骤都在干净的环境中进行，从而通过避免将晶片暴露在大气中并在步骤之间可能的污染来提高产量。

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