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1. 发明授权

US09070432B2 Negative bitline boost scheme for SRAM write-assist 有权
标题翻译： SRAM写入辅助负位线提升方案
公开(公告)号：US09070432B2
公开(公告)日：2015-06-30
申请号：US14077263
申请日：2013-11-12
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wei-jer Hsieh , Yangsyu Lin , Hsiao Wen Lu , Chiting Cheng , Jonathan Tsung-Yung Chang
IPC分类号： G11C11/00 , G11C7/12 , G11C11/419
CPC分类号： G11C11/419 , G11C7/12
摘要： A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.
摘要翻译：一种器件包括耦合在位线电压节点和接地节点之间的晶体管开关和耦合到晶体管开关的栅极节点的升压信号电路，其中升压信号电路响应于写使能信号而提供升压信号。该装置还包括与第一延迟元件串联的第一延迟元件和第一电容器。第一电容器具有耦合到位线电压节点的第一端和通过第一延迟元件耦合到栅极节点的第二端。

2. 发明授权

US09437281B2 Negative bitline boost scheme for SRAM write-assist 有权
公开(公告)号：US09437281B2
公开(公告)日：2016-09-06
申请号：US14727931
申请日：2015-06-02
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Wei-Jer Hsieh , Yangsyu Lin , Hsiao Wen Lu , Chiting Cheng , Jonathan Tsung-Yung Chang
IPC分类号： G11C5/14 , G11C11/419 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12
摘要： A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

3. 发明授权

US09305635B2 High density memory structure 有权
标题翻译：高密度存储器结构
公开(公告)号：US09305635B2
公开(公告)日：2016-04-05
申请号：US14068003
申请日：2013-10-31
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yangsyu Lin , Hsiao Wen Lu , Chiting Cheng , Jonathan Tsung-Yung Chang
IPC分类号： G11C5/06 , G11C11/419 , G11C7/18
CPC分类号： G11C11/419 , G11C7/18
摘要： A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines.
摘要翻译：半导体存储器包括多个子存储体，每个子存储体包括连接到一组局部位线的一行或多行存储器位单元，其中子存储体共享用于从/向存储器读/写数据的全局位线集合子库的位单元。半导体存储器芯片还包括用于每个子存储体的多个开关元件，其中每个开关元件连接子库中对应的一个存储单元的局部位线和全局位线，用于数据传输在本地位线和全局位线之间。半导体存储器芯片还包括多个存储体选择信号线，每条存储体选择信号线连接到相应的一个子存储体中的开关元件，其中存储体选择信号线传送多个存储体选择信号以选择一个子存储体用于数据局部位线与全局位线之间的传输。

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