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1. 发明授权

US10861790B2 Power strap structure for high performance and low current density 有权
公开(公告)号：US10861790B2
公开(公告)日：2020-12-08
申请号：US16216075
申请日：2018-12-11
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Kam-Tou Sio , Pin-Dai Sue , Ru-Gun Liu , Shih-Wei Peng , Wen-Hao Chen , Yung-Sung Yen , Chun-Kuang Chen
IPC分类号： H01L23/528 , H01L27/092 , H01L21/8238 , H01L23/522 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L21/768
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.

2. 发明申请

US20200328148A1 Semiconductor Device and Layout Design Thereof 审中-公开
公开(公告)号：US20200328148A1
公开(公告)日：2020-10-15
申请号：US16913697
申请日：2020-06-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Li-Chun Tien , Pin-Dai Sue
IPC分类号： H01L23/522 , H01L27/118 , H01L27/02
摘要： A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

3. 发明授权

US10163880B2 Integrated circuit and method of fabricating the same 有权
公开(公告)号：US10163880B2
公开(公告)日：2018-12-25
申请号：US15145354
申请日：2016-05-03
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Pin-Dai Sue , Li-Chun Tien
IPC分类号： H01L27/02 , G06F17/50 , H01L27/092 , H01L29/423 , H01L27/118
摘要： A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

4. 发明申请

US20180174967A1 POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY 审中-公开
公开(公告)号：US20180174967A1
公开(公告)日：2018-06-21
申请号：US15898882
申请日：2018-02-19
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Kam-Tou Sio , Pin-Dai Sue , Ru-Gun Liu , Shih-Wei Peng , Wen-Hao Chen , Yung-Sung Yen , Chun-Kuang Chen
IPC分类号： H01L23/528 , H01L21/8238 , H01L27/092
CPC分类号： H01L23/5286 , H01L21/823431 , H01L21/823821 , H01L21/823871 , H01L21/845 , H01L23/522 , H01L23/5222 , H01L27/0886 , H01L27/0924 , H01L27/1211
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and middle-end-of-the-line (MEOL) structures extending in a first direction over an active area of a substrate. The MEOL structures are interleaved between the gate structures along a second direction. The method further forms a power rail and a first metal wire extending in the second direction. The first metal wire is over the MEOL structures. A double patterning process is performed to form second and third metal wires extending in the first direction over the first metal wire and separated in the second direction. The second metal wire is cut according to a first cut region of a first cut mask to define a first metal strap connecting a first one of the MEOL structures to the power rail.

5. 发明授权

US09202696B2 Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits 有权
标题翻译：用于设计防止半导体集成电路中的等离子体感应栅介质损伤的天线单元的方法
公开(公告)号：US09202696B2
公开(公告)日：2015-12-01
申请号：US14511932
申请日：2014-10-10
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Jen-Hang Yang , Chun-Fu Chen , Pin-Dai Sue , Hui-Zhong Zhuang
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/02 , H01L27/06 , H01L21/283 , H01L21/768 , H01L23/60 , H01L27/08
CPC分类号： H01L21/28008 , H01L21/283 , H01L21/76895 , H01L23/60 , H01L27/0207 , H01L27/0629 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
摘要翻译：提供了一种用于防止等离子体增强的栅极介质故障的天线单元。天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。多晶硅引线可以是一组并联的嵌套多晶硅引线之一。虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。二极管与形成有半导体衬底的半导体衬底形成。源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。

6. 发明授权

US11088067B2 Semiconductor device and layout design thereof 有权
公开(公告)号：US11088067B2
公开(公告)日：2021-08-10
申请号：US16913697
申请日：2020-06-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Li-Chun Tien , Pin-Dai Sue
IPC分类号： H01L23/522 , H01L27/118 , H01L27/02
摘要： A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

7. 发明申请

US20190122987A1 POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY 审中-公开
公开(公告)号：US20190122987A1
公开(公告)日：2019-04-25
申请号：US16216075
申请日：2018-12-11
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Kam-Tou Sio , Pin-Dai Sue , Ru-Gun Liu , Shih-Wei Peng , Wen-Hao Chen , Yung-Sung Yen , Chun-Kuang Chen
IPC分类号： H01L23/528 , H01L27/12 , H01L27/088 , H01L21/84 , H01L21/8234 , H01L27/092 , H01L23/522 , H01L21/8238
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.

8. 发明授权

US11476250B2 Double rule integrated circuit layouts for a dual transmission gate 有权
公开(公告)号：US11476250B2
公开(公告)日：2022-10-18
申请号：US17120839
申请日：2020-12-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Wei Peng , Hui-Zhong Zhuang , Jiann-Tyng Tzeng , Li-Chun Tien , Pin-Dai Sue , Wei-Cheng Lin
IPC分类号： H01L21/70 , H01L27/092 , H03K17/687
摘要： Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

9. 发明授权

US11239228B2 Integrated circuit layout and method of configuring the same 有权
公开(公告)号：US11239228B2
公开(公告)日：2022-02-01
申请号：US16921894
申请日：2020-07-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Pin-Dai Sue , Li-Chun Tien
IPC分类号： G06F7/50 , H01L27/02 , H01L27/088 , H01L27/092 , G06F30/392 , H01L27/118 , G06F111/20 , G06F119/18
摘要： An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

10. 发明申请

US20200006338A1 DOUBLE RULE INTEGRATED CIRCUIT LAYOUTS FOR A DUAL TRANSMISSION GATE 审中-公开
公开(公告)号：US20200006338A1
公开(公告)日：2020-01-02
申请号：US16021847
申请日：2018-06-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Wei PENG , Hui-Zhong Zhuang , Jiann-Tyng Tzeng , Li-Chun Tien , Pin-Dai Sue , Wei-Cheng Lin
IPC分类号： H01L27/092 , H03K17/687
摘要： Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

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