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1. 发明授权

US11088092B2 Via rail solution for high power electromigration 有权
公开(公告)号：US11088092B2
公开(公告)日：2021-08-10
申请号：US16106395
申请日：2018-08-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kam-Tou Sio , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Ru-Gun Liu , Wen-Hao Chen
IPC分类号： H01L23/528 , H01L23/522 , H01L23/00 , H01L23/485 , H01L21/8234 , H01L23/532
摘要： The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.

2. 发明授权

US10509887B2 Must-join pin sign-off method 有权
公开(公告)号：US10509887B2
公开(公告)日：2019-12-17
申请号：US15908353
申请日：2018-02-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sheng-Hsiung Chen , Ming-Huei Tsai , Shao-Huan Wang , Shu-Yu Chen , Wen-Hao Chen , Chun-Chen Chen
IPC分类号： G06F17/50 , H01L21/67
摘要： The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.

3. 发明申请

US20180358309A1 VIA RAIL SOLUTION FOR HIGH POWER ELECTROMIGRATION 审中-公开
公开(公告)号：US20180358309A1
公开(公告)日：2018-12-13
申请号：US16106395
申请日：2018-08-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kam-Tou Sio , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Ru-Gun Liu , Wen-Hao Chen
IPC分类号： H01L23/00 , H01L23/528 , H01L23/485 , H01L23/522 , H01L21/8234 , H01L23/532
CPC分类号： H01L23/564 , H01L21/823475 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295
摘要： The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.

4. 发明授权

US09799602B2 Integrated circuit having a staggered fishbone power network 有权
公开(公告)号：US09799602B2
公开(公告)日：2017-10-24
申请号：US14983797
申请日：2015-12-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kuang-Hung Chang , Wen-Hao Chen , Yuan-Te Hou , Kumar Lalgudi
IPC分类号： H01L23/00 , H01L21/76 , H01L23/528 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5283 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5286
摘要： An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first plurality of ribs formed on a second conductive layer of the integrated circuit, the first plurality of ribs run parallel to one another in a second direction that is orthogonal to the first direction and overlap respective portions of the first spine; a first plurality of interlayer vias formed between the first and second conductive layers, each of the plurality of interlayer vias electrically couple respective ones of the first plurality of ribs to the first spine at the respective portions of overlap; and a plurality of signal lines formed on the second conductive layer and running parallel to one another in the second direction.

5. 发明申请

US20170117272A1 Via Rail Solution for High Power Electromigration 审中-公开
公开(公告)号：US20170117272A1
公开(公告)日：2017-04-27
申请号：US15213506
申请日：2016-07-19
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kam-Tou Sio , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Ru-Gun Liu , Wen-Hao Chen
IPC分类号： H01L27/088 , H01L23/528 , H01L23/00 , H01L23/535
CPC分类号： H01L23/564 , H01L21/823475 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295
摘要： The present disclosure relates to an integrated circuit having a via rail that prevents reliability concerns such as electro-migration. In some embodiments, the integrated circuit has a first plurality of conductive contacts arranged over a semiconductor substrate. A first metal interconnect wire is arranged over the first plurality of conductive contacts, and a second metal interconnect wire is arranged over the first metal interconnect wire. A via rail is arranged over the first metal interconnect wire and electrically couples the first metal interconnect wire and the second metal interconnect wire. The via rail has a length that continuously extends over two or more of the plurality of conductive contacts. The length of via rail provides for an increased cross-sectional area both between the first metal interconnect wire and the second metal interconnect wire and along a length of the via rail, thereby mitigating electro-migration within the integrated circuit.

6. 发明授权

US09563731B2 Cell boundaries for self aligned multiple patterning abutments 有权
标题翻译：自对准多图案化基台的单元边界
公开(公告)号：US09563731B2
公开(公告)日：2017-02-07
申请号：US14210490
申请日：2014-03-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Li-Chun Tien , Pin-Dai Sue , Ching Hsiang Chang , Wen-Hao Chen , Cheng-I Huang
IPC分类号： G06F17/50 , G03F7/20 , G03F1/70
CPC分类号： G06F17/5068 , G03F1/70 , G03F7/70433 , G03F7/70466
摘要： A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.
摘要翻译：公开了一种确定单元布局的系统和方法。所述方法包括接收与预定电路设计相对应的电路设计，所述电路设计具有第一组单元并邻接所述第一组单元中的相邻单元，所述邻接单元在其间具有第一边界图案。基于第一边界图案中的信号线的数量或位置，第一边界图案与第二边界图案交换。然后可以确定用于图案化处理的单元格布局，单元布局包括第二边界图案。

7. 发明授权

US09262570B2 Layout boundary method 有权
标题翻译：布局边界法
公开(公告)号：US09262570B2
公开(公告)日：2016-02-16
申请号：US13919037
申请日：2013-06-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Wen-Hao Chen , Ho Che Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.
摘要翻译：本公开的一些实施例涉及实现与多图案化过程兼容的布局的方法和装置。两个或多个单元电池被构造成具有满足多图案化工艺的性质的布局，并且分解成两种或更多种颜色以支持多图案化工艺。活动布局特征与两个单位单元之间的共享边界处的虚拟线合并。在共享边界处的两个活动布局特征之间短路的情况下，自动布局后方法可以重新排列共享边界附近的布局特征，以分离活动布局特征以实现单元功能，同时满足多图案化属性。

8. 发明授权

US09223924B2 Method and system for multi-patterning layout decomposition 有权
标题翻译：多图案布局分解的方法和系统
公开(公告)号：US09223924B2
公开(公告)日：2015-12-29
申请号：US14043890
申请日：2013-10-02
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Chin-Chang Hsu , Yuan-Te Hou , Godina Ho , Wen-Hao Chen , Wen-Ju Yang
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G06F17/5081 , G03F1/00 , G03F1/36 , G03F1/70 , G03F7/70283 , G03F7/70466 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.
摘要翻译：集成电路的单层布局的一部分是多图案化的。用于布局分解的方法包括确定相邻图案对之间的间隔，以及生成具有多个子图的冲突图，其中相应的顶点对应于每个相应的子图。每个相应子图中的图案被划分为至少第一组和第二组，其中的每一组被分配为通过第一掩模或第二掩模中的分别不同的一个在单层上被图案化。该方法还包括在处理器中基于预定的一组标准来确定每个相应子图中的多个模式中的颜色规则违规的计数; 并且在每个子图中，将子图中的第一组图案分配给第一掩码或第二掩码中的一个，导致颜色规则违规的较小数量。

9. 发明授权

US08977991B2 Method and system for replacing a pattern in a layout 有权
标题翻译：用于替换布局中的图案的方法和系统
公开(公告)号：US08977991B2
公开(公告)日：2015-03-10
申请号：US14068006
申请日：2013-10-31
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Huang-Yu Chen , Yuan-Te Hou , Chung-Min Fu , Chung-Hsing Wang , Wen-Hao Chen , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.
摘要翻译：接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案被包括在第二个光掩模中。所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。输出表示剩余的第一图案和替换图案的数据。

10. 发明申请

US20140282344A1 LAYOUT BOUNDARY METHOD 有权
标题翻译：布局边界方法
公开(公告)号：US20140282344A1
公开(公告)日：2014-09-18
申请号：US13919037
申请日：2013-06-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Wen-Hao Chen , Ho Che Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.
摘要翻译：本公开的一些实施例涉及实现与多图案化过程兼容的布局的方法和装置。两个或多个单元电池被构造成具有满足多图案化工艺的性质的布局，并且分解成两种或更多种颜色以支持多图案化工艺。活动布局特征与两个单位单元之间的共享边界处的虚拟线合并。在共享边界处的两个活动布局特征之间短路的情况下，自动布局后方法可以重新排列共享边界附近的布局特征，以分离活动布局特征以实现单元功能，同时满足多图案化属性。

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