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1. 发明授权

US11183394B2 Structure and method to expose memory cells with different sizes 有权
公开(公告)号：US11183394B2
公开(公告)日：2021-11-23
申请号：US16916415
申请日：2020-06-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sheng-Chau Chen , Cheng-Tai Hsiao , Cheng-Yuan Tsai , Hsun-Chung Kuang , Yao-Wen Chang
IPC分类号： H01L45/00 , H01L21/311 , H01L21/3105 , H01L43/02 , H01L23/528 , H01L43/08 , H01L43/12
摘要： A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends along sidewalls of the bottom electrode, the switching dielectric, and the top electrode and an upper surface of a lower dielectric layer. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The the sidewall spacer layer separates the lower etch stop layer from the lower dielectric layer.

2. 发明授权

US11164836B2 Film scheme for bumping 有权
公开(公告)号：US11164836B2
公开(公告)日：2021-11-02
申请号：US16549013
申请日：2019-08-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yao-Wen Chang , Chern-Yow Hsu , Cheng-Yuan Tsai , Kong-Beng Thei
IPC分类号： H01L29/417 , H01L23/00 , H01L21/288 , H01L21/311
摘要： A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

3. 发明申请

US20210098398A1 FILM STRUCTURE FOR BOND PAD 有权
公开(公告)号：US20210098398A1
公开(公告)日：2021-04-01
申请号：US16589497
申请日：2019-10-01
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Julie Yang , Chii-Ming Wu , Tzu-Chung Tsai , Yao-Wen Chang
IPC分类号： H01L23/00
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.

4. 发明授权

US10275559B2 Method for legalizing mixed-cell height standard cells of IC 有权
公开(公告)号：US10275559B2
公开(公告)日：2019-04-30
申请号：US15355431
申请日：2016-11-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chao-Hung Wang , Yen-Yi Wu , Shih-Chun Chen , Yao-Wen Chang , Meng-Kai Hsu
IPC分类号： G06F17/50
摘要： A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.

5. 发明授权

US10163651B1 Structure and method to expose memory cells with different sizes 有权
公开(公告)号：US10163651B1
公开(公告)日：2018-12-25
申请号：US15883748
申请日：2018-01-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sheng-Chau Chen , Cheng-Tai Hsiao , Cheng-Yuan Tsai , Hsun-Chung Kuang , Yao-Wen Chang
IPC分类号： H01L45/00 , H01L21/311 , H01L21/3105 , H01L43/02 , H01L23/528 , H01L43/08
摘要： A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided.

6. 发明申请

US20180151527A1 Film Scheme for Bumping 审中-公开
公开(公告)号：US20180151527A1
公开(公告)日：2018-05-31
申请号：US15711045
申请日：2017-09-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yao-Wen Chang , Chern-Yow Hsu , Cheng-Yuan Tsai , Kong-Beng Thei
IPC分类号： H01L23/00 , H01L21/311 , H01L21/288
CPC分类号： H01L24/13 , H01L21/288 , H01L21/31116 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02175 , H01L2224/0345 , H01L2224/03452 , H01L2224/0391 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05186 , H01L2224/05567 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/10145 , H01L2224/11424 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1301 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13021 , H01L2224/13078 , H01L2224/13083 , H01L2224/13144 , H01L2224/13155 , H01L2224/13157 , H01L2224/13166 , H01L2224/13169 , H01L2224/13173 , H01L2224/13176 , H01L2224/13178 , H01L2224/13186 , H01L2924/01022 , H01L2924/01027 , H01L2924/01073 , H01L2924/04941 , H01L2924/04953 , H01L2924/013 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029
摘要： A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

7. 发明申请

US20170110533A1 MIM/RRAM STRUCTURE WITH IMPROVED CAPACITANCE AND REDUCED LEAKAGE CURRENT 有权
公开(公告)号：US20170110533A1
公开(公告)日：2017-04-20
申请号：US15392169
申请日：2016-12-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Jian-Shiou Huang , Yao-Wen Chang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC分类号： H01L49/02 , H01L21/02 , H01L23/522
CPC分类号： H01L28/40 , H01L21/02112 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02266 , H01L23/5223 , H01L29/88 , H01L45/08 , H01L45/10
摘要： Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.

8. 发明授权

US09425061B2 Buffer cap layer to improve MIM structure performance 有权
标题翻译：缓冲帽层，提高MIM结构性能
公开(公告)号：US09425061B2
公开(公告)日：2016-08-23
申请号：US14289739
申请日：2014-05-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yao-Wen Chang , Jian-Shiou Huang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC分类号： H01L45/00 , H01L21/3105 , H01L49/02 , H01L21/02
CPC分类号： H01L21/31051 , H01L21/0214 , H01L21/0217 , H01L21/02244 , H01L21/02255 , H01L21/02271 , H01L21/02274 , H01L28/60 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16
摘要： The present disclosure relates to method of forming a MIM (metal-insulator-metal) structure having a buffer cap layer that reduces stress induced by an overlying stress-inducing protective layer, and an associated apparatus. The method is performed by forming a lower conductive layer over a semiconductor substrate, forming a dielectric layer over the lower conductive layer, and forming an upper conductive layer over the dielectric layer. A buffer cap layer is formed over the upper conductive layer and a stress-inducing protective layer is formed onto the buffer cap layer. The buffer cap layer reduces a stress induced onto the upper conductive layer by the stress-inducing protective layer, thereby reducing leakage current between the lower and upper conductive layers.
摘要翻译：本公开内容涉及形成具有缓冲覆盖层的MIM（金属 - 绝缘体 - 金属）结构的方法，该缓冲覆盖层减少由上覆的应力诱导保护层引起的应力，以及相关联的装置。该方法通过在半导体衬底上形成下导电层，在下导电层上形成电介质层，并在电介质层上形成上导电层。在上导电层之上形成缓冲覆盖层，并且在缓冲覆盖层上形成应力诱导保护层。缓冲覆盖层通过应力诱导保护层降低在上导电层上的应力，从而减少下导电层和上导电层之间的漏电流。

9. 发明申请

US20160049583A1 MEMORY STRUCTURE HAVING TOP ELECTRODE WITH PROTRUSION 有权
标题翻译：具有顶端电极的记忆结构
公开(公告)号：US20160049583A1
公开(公告)日：2016-02-18
申请号：US14457170
申请日：2014-08-12
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Jian-Shiou Huang , Yao-Wen Chang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC分类号： H01L45/00
CPC分类号： H01L45/1273 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1666 , H01L45/1675
摘要： The present disclosure relates to an RRAM (resistive random access memory) cell having a top electrode with a geometry configured to improve the electric performance of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a lower insulating layer with a micro-trench located over a lower metal interconnect layer disposed within a lower inter-level dielectric (ILD) layer that overlies a semiconductor substrate. A bottom electrode is disposed over the micro-trench, and a dielectric data storage layer is located over the bottom electrode. A top electrode is disposed over the dielectric data storage layer. The top electrode has a protrusion that extends outward from a bottom surface of the top electrode at a position overlying the micro-trench. The protrusion generates a region having an enhanced electric field within the dielectric data storage layer, which improves performance of the RRAM cell.
摘要翻译：本公开涉及一种具有顶部电极的RRAM（电阻随机存取存储器）单元，其具有被配置为改善RRAM单元的电性能的几何形状以及相关联的形成方法。在一些实施例中，RRAM单元具有下绝缘层，其中微沟槽位于布置在覆盖半导体衬底的下层间电介质（ILD）层内的下金属互连层上。底部电极设置在微沟槽上方，并且电介质数据存储层位于底部电极之上。顶部电极设置在电介质数据存储层上。顶部电极具有从顶部电极的底表面向外延伸的突出部，该突出部位于覆盖微沟槽的位置。突起产生在电介质数据存储层内具有增强电场的区域，这提高了RRAM单元的性能。

10. 发明授权

US11527713B2 Top electrode via with low contact resistance 有权
公开(公告)号：US11527713B2
公开(公告)日：2022-12-13
申请号：US16921133
申请日：2020-07-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Bi-Shen Lee , Hai-Dang Trinh , Hsun-Chung Kuang , Tzu-Chung Tsai , Yao-Wen Chang
IPC分类号： H01L45/00
摘要： The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

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