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1. 发明授权

US09373704B2 Multiple-gate semiconductor device and method 有权
公开(公告)号：US09373704B2
公开(公告)日：2016-06-21
申请号：US14552237
申请日：2014-11-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tung Ying Lee , Li-Wen Weng , Chien-Tai Chan , Da-Wen Lin , Hsien-Chin Lin
IPC分类号： H01L29/66 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/823431 , H01L27/0886 , H01L29/785
摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

2. 发明申请

US20130230958A1 Multiple-Gate Semiconductor Device and Method 有权
公开(公告)号：US20130230958A1
公开(公告)日：2013-09-05
申请号：US13863963
申请日：2013-04-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tung Ying Lee , Li-Wen Weng , Chien-Tai Chan , Da-Wen Lin , Hsien-Chin Lin
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/823431 , H01L27/0886 , H01L29/785
摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

3. 发明授权

US09659776B2 Doping for FinFET 有权
公开(公告)号：US09659776B2
公开(公告)日：2017-05-23
申请号：US15153585
申请日：2016-05-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Kai Chen , Tsung-Hung Lee , Han-Pin Chung , Shih-Syuan Huang , Chun-Fu Cheng , Chien-Tai Chan , Kuang-Yuan Hsu , Hsien-Chin Lin , Ka-Hing Fung
IPC分类号： H01L23/04 , H01L21/225 , H01L29/78 , H01L29/06 , H01L21/8238 , H01L21/84 , H01L29/66
CPC分类号： H01L21/2251 , H01L21/2255 , H01L21/823821 , H01L21/845 , H01L29/0657 , H01L29/6656 , H01L29/66795 , H01L29/66803 , H01L29/7851
摘要： First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.

4. 发明授权

US09362404B2 Doping for FinFET 有权
公开(公告)号：US09362404B2
公开(公告)日：2016-06-07
申请号：US14186910
申请日：2014-02-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Kai Chen , Tsung-Hung Lee , Han-Pin Chung , Shih-Syuan Huang , Chun-Fu Cheng , Chien-Tai Chan , Kuang-Yuan Hsu , Hsien-Chin Lin , Ka-Hing Fung
IPC分类号： H01L29/00 , H01L29/78 , H01L29/06 , H01L21/225
CPC分类号： H01L21/2251 , H01L21/2255 , H01L21/823821 , H01L21/845 , H01L29/0657 , H01L29/6656 , H01L29/66795 , H01L29/66803 , H01L29/7851
摘要： First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.

5. 发明授权

US08895383B2 Multiple-gate semiconductor device and method 有权
标题翻译：多栅半导体器件及方法
公开(公告)号：US08895383B2
公开(公告)日：2014-11-25
申请号：US13863963
申请日：2013-04-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tung Ying Lee , Li-Wen Weng , Chien-Tai Chan , Da-Wen Lin , Hsien-Chin Lin
IPC分类号： H01L21/8238 , H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/823431 , H01L27/0886 , H01L29/785
摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.
摘要翻译：公开了一种用于制造多栅极半导体器件的系统和方法。一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

6. 发明申请

US20160260610A1 Doping for FinFET 审中-公开
公开(公告)号：US20160260610A1
公开(公告)日：2016-09-08
申请号：US15153585
申请日：2016-05-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Kai Chen , Tsung-Hung Lee , Han-Pin Chung , Shih-Syuan Huang , Chun-Fu Cheng , Chien-Tai Chan , Kuang-Yuan Hsu , Hsien-Chin Lin , Ka-Hing Fung
IPC分类号： H01L21/225 , H01L29/66
CPC分类号： H01L21/2251 , H01L21/2255 , H01L21/823821 , H01L21/845 , H01L29/0657 , H01L29/6656 , H01L29/66795 , H01L29/66803 , H01L29/7851
摘要： First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.

7. 发明申请

US20150243739A1 Doping for FinFET 有权
标题翻译：掺杂FinFET
公开(公告)号：US20150243739A1
公开(公告)日：2015-08-27
申请号：US14186910
申请日：2014-02-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Kai Chen , Tsung-Hung Lee , Han-Pin Chung , Shih-Syuan Huang , Chun-Fu Cheng , Chien-Tai Chan , Kuang-Yuan Hsu , Hsien-Chin Lin , Ka-Hing Fung
IPC分类号： H01L29/36 , H01L29/06 , H01L21/225 , H01L29/78
CPC分类号： H01L21/2251 , H01L21/2255 , H01L21/823821 , H01L21/845 , H01L29/0657 , H01L29/6656 , H01L29/66795 , H01L29/66803 , H01L29/7851
摘要： First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.
摘要翻译：从基板形成第一和第二散热片。第一层形成在第一鳍上。第一层包括第一掺杂剂。第一层的一部分从第一鳍片的尖端部分去除。第二层形成在第二鳍上。第二层包括第二掺杂剂。第一和第二掺杂剂之一是p型掺杂剂，第一和第二掺杂剂中的另一种是n型掺杂剂。第二层的一部分从第二鳍的尖端部分移除。执行固相扩散处理以将第一掺杂剂扩散到第一鳍片的非尖端部分中，并将第二掺杂剂扩散到第二鳍片的非尖端部分。

8. 发明申请

US20150079753A1 Multiple-Gate Semiconductor Device and Method 审中-公开
标题翻译：多栅极半导体器件及方法
公开(公告)号：US20150079753A1
公开(公告)日：2015-03-19
申请号：US14552237
申请日：2014-11-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tung Ying Lee , Li-Wen Weng , Chien-Tai Chan , Da-Wen Lin , Hsien-Chin Lin
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/823431 , H01L27/0886 , H01L29/785
摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.
摘要翻译：公开了一种用于制造多栅极半导体器件的系统和方法。一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

9. 发明申请

US20140061817A1 Hybrid Gate Process for Fabricating FinFET Device 有权
标题翻译：用于制造FinFET器件的混合栅极工艺
公开(公告)号：US20140061817A1
公开(公告)日：2014-03-06
申请号：US14083533
申请日：2013-11-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Tian-Choy Gan , Hsien-Chin Lin , Chia-Pin Lin , Shyue-Shyh Lin , Li-Shiun Chen , Shin Hsien Liao
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/8238 , H01L29/66795 , H01L29/785
摘要： Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片，在第一和第二鳍片上形成第一和第二栅极结构，第一和第二栅极结构包括第一和第二多晶硅栅极，在所述衬底上形成层间电介质（ILD），在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极，形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极，从而形成第一沟槽，去除掩模，部分地移除第一多晶硅栅极，从而形成第二沟槽，形成部分填充第一和第二沟槽的功函数金属层，形成填充第一和第二沟槽的剩余部分的填充金属层沟槽，并且去除第一和第二沟槽外的金属层。

10. 发明授权

US08994116B2 Hybrid gate process for fabricating FinFET device 有权
标题翻译：用于制造FinFET器件的混合栅极工艺
公开(公告)号：US08994116B2
公开(公告)日：2015-03-31
申请号：US14083533
申请日：2013-11-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tian-Choy Gan , Hsien-Chin Lin , Chia-Pin Lin , Shyue-Shyh Lin , Li-Shiun Chen , Shin Hsien Liao
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/8238 , H01L29/66795 , H01L29/785
摘要： Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片，在第一和第二鳍片上形成第一和第二栅极结构，第一和第二栅极结构包括第一和第二多晶硅栅极，在所述衬底上形成层间电介质（ILD），在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极，形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极，从而形成第一沟槽，去除掩模，部分地移除第一多晶硅栅极，从而形成第二沟槽，形成部分填充第一和第二沟槽的功函数金属层，形成填充第一和第二沟槽的剩余部分的填充金属层沟槽，并且去除第一和第二沟槽外的金属层。

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