专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10002829B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10002829B2
公开(公告)日：2018-06-19
申请号：US14954207
申请日：2015-11-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Hao Chen , Chen-Hsiang Hsu , Hung-Chih Lin , Ching-Nen Peng , Mill-Jer Wang
IPC分类号： H01L23/528 , G01R19/00 , G01R31/28 , H01L23/31 , H01L23/00 , H01L25/065 , H01L23/498
CPC分类号： H01L23/528 , G01R19/0092 , G01R31/2831 , G01R31/2884 , G01R31/2896 , H01L22/32 , H01L23/3107 , H01L23/49816 , H01L23/49827 , H01L24/06 , H01L24/09 , H01L24/14 , H01L24/17 , H01L25/0655 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/24137 , H01L2924/18162 , H01L2924/2064
摘要： A semiconductor device is provided which comprises a semiconductive substrate and an interconnect on the substrate. The interconnect comprises a dielectric in an upper most level of the interconnect and a plurality of conductive pads where each of the plurality of conductive pads is at least partially exposed from the dielectric. The interconnect further includes a current sensor electrically coupled with at least one of the plurality of conductive pads.

2. 发明授权

US09513332B2 Probe card partition scheme 有权
标题翻译：探测卡分区方案
公开(公告)号：US09513332B2
公开(公告)日：2016-12-06
申请号：US14459801
申请日：2014-08-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Sandeep Kumar Goel , Mill-Jer Wang
IPC分类号： G01R31/00 , G01R31/28 , G01R1/04 , G01R1/073 , G01R31/319
CPC分类号： G01R31/2889 , G01R1/0408 , G01R1/07342 , G01R31/31908
摘要： A method of testing an integrated circuit die comprises partitioning a first probe card partition layout of the integrated circuit die having one or more sections comprising a first quantity of section types into a second probe card partition layout having a greater quantity of sections comprising a second quantity of section types, the second quantity of section types being less than the first quantity of section types. The method also comprises using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type included in the second probe card partition layout.
摘要翻译：一种测试集成电路管芯的方法包括将具有一个或多个部分的集成电路管芯的第一探针卡分隔布局分成包括第一数量的部分类型到具有更大数量的部分的第二探针卡分配布局，所述部分包括第二数量的截面类型，第二数量的截面类型小于第一数量的截面类型。该方法还包括使用一个或多个探针卡来测试第二探针卡分区布局中的部分，所述一个或多个探针卡中的每一个具有与包括在每个部分类型之一的测试接触图案相对应的测试接触图案第二个探针卡分区布局。

3. 发明申请

US20140176165A1 Apparatus for Three Dimensional Integrated Circuit Testing 有权
标题翻译：三维集成电路测试装置
公开(公告)号：US20140176165A1
公开(公告)日：2014-06-26
申请号：US13724004
申请日：2012-12-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang , Chung-Sheng Yuan , Ching-Fang Chen , Wen-Wen Hsieh , Meng-Lin Chung
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R1/07378
摘要： A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.
摘要翻译：三维集成电路测试装置包括：探针卡，被配置为将三维集成电路的测试装置与具有多个测试模块的自动测试设备板耦合，其中所述探针卡包括多个已知的三维集成电路的良好裸片，三维集成电路的多个互连和多个探针触点，其中探针触点被配置为将探针卡与被测器件的测试触点耦合三维集成电路。

4. 发明授权

US11335672B2 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US11335672B2
公开(公告)日：2022-05-17
申请号：US16937343
申请日：2020-07-23
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Hsiang-Tai Lu , Shuo-Mao Chen , Mill-Jer Wang , Feng-Cheng Hsu , Chao-Hsiang Yang , Shin-Puu Jeng , Cheng-Yi Hong , Chih-Hsien Lin , Dai-Jang Chen , Chen-Hua Lin
IPC分类号： H01L25/00 , H01L23/538 , H01L23/31 , H01L23/00 , H01L25/10 , H01L21/48 , H01L21/56 , H01L21/66 , H01L23/498 , H01L23/522 , H01L23/053
摘要： A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

5. 发明授权

US11199576B2 Probe head structure of probe card and testing method 有权
公开(公告)号：US11199576B2
公开(公告)日：2021-12-14
申请号：US16390779
申请日：2019-04-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Cheng Hsu , Mill-Jer Wang
IPC分类号： G01R31/28
摘要： A probe head and methods of testing a device using a probe head are provided. The probe head includes a first end connected to a first substrate. The first substrate is configured to be connected to a test head. The probe head also includes second end having a first inner recess surrounded by a first protrusion and a first plurality of probe needles connected to the first protrusion.

6. 发明申请

US20210096173A1 SYSTEM AND METHOD FOR SEMICONDUCTOR DEVICE TESTING 有权
公开(公告)号：US20210096173A1
公开(公告)日：2021-04-01
申请号：US16867999
申请日：2020-05-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hao Chen , Mill-Jer Wang
IPC分类号： G01R31/28
摘要： A testing system includes a load board that includes a first circuit board, a first external connector attached to the first circuit board, and a thermal module configured to hold a system-on-wafer structure including a connector and a socket, a connector structure including a second circuit board, wherein the second circuit board is electrically connected to the first external connector, and a second external connector configured to connect to the connector of the system-on-wafer structure, and a test structure configured to connect to the socket of the system-on-wafer structure, the test structure including a third circuit board and pins, wherein adjacent pairs of pins of the test structure are electrically coupled through the third circuit board to form a continuous conductive path extending alternately between the system-on-wafer structure and the adjacent pairs of pins of the test structure.

7. 发明授权

US09880201B2 Systems for probing semiconductor wafers 有权
公开(公告)号：US09880201B2
公开(公告)日：2018-01-30
申请号：US14601671
申请日：2015-01-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
IPC分类号： G01R31/00 , G01R1/073 , G01R35/00 , G01R31/28 , G01R31/26 , G01R31/319 , G01R31/11
CPC分类号： G01R1/07307 , G01R31/11 , G01R31/2601 , G01R31/2891 , G01R31/3191 , G01R35/005
摘要： A wafer probing system includes a plurality of contacting pins connected to a test head. The system further includes a probe card electrically connectable with the test head, where the probe card includes a circuit board having a plurality of contact pads on opposite sides of the circuit board.

8. 发明授权

US09448285B2 Method and apparatus of wafer testing 有权
标题翻译：晶圆测试的方法和装置
公开(公告)号：US09448285B2
公开(公告)日：2016-09-20
申请号：US13915409
申请日：2013-06-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Shang-Ju Lee
IPC分类号： G01R31/00 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318511 , G01R31/2889 , G01R31/318513
摘要： A system for testing a wafer includes a probe card and a wafer. The probe card includes at least one first probe site and at least one second probe site. The wafer includes a plurality of dies. The at least one first probe site is arranged for a first test, and the at least one second probe site is arranged for a second test. Each of the plurality of dies corresponds to first probe pads and second probe pads. Each of the at least one first probe site is arranged to touch the first probe pads of each of the plurality of dies. Each of the at least one second probe site is arranged to touch the second probe pads of each of the plurality of dies.
摘要翻译：用于测试晶片的系统包括探针卡和晶片。探针卡包括至少一个第一探针位点和至少一个第二探针位点。晶片包括多个管芯。所述至少一个第一探针位置被布置用于第一测试，并且所述至少一个第二探针位置被布置用于第二测试。多个管芯中的每一个对应于第一探针焊盘和第二探针焊盘。所述至少一个第一探针位置中的每一个被布置成接触所述多个管芯中的每一个的所述第一探针焊盘。所述至少一个第二探针位置中的每一个被布置成接触所述多个管芯中的每一个的所述第二探针焊盘。

9. 发明授权

US09341671B2 Testing holders for chip unit and die package 有权
公开(公告)号：US09341671B2
公开(公告)日：2016-05-17
申请号：US13830525
申请日：2013-03-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Mill-Jer Wang , Kuo-Chuan Liu , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
IPC分类号： G01R31/00 , G01R31/28 , G01R1/04 , G01R31/3185
CPC分类号： G01R31/2893 , G01R1/0483 , G01R1/06722 , G01R31/2867 , G01R31/2875 , G01R31/318513
摘要： A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

10. 发明申请

US20220381817A1 TESTING MODULE AND TESTING METHOD USING THE SAME 有权
公开(公告)号：US20220381817A1
公开(公告)日：2022-12-01
申请号：US17884487
申请日：2022-08-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hao Chen , Mill-Jer Wang
IPC分类号： G01R31/27 , G01R1/04
摘要： A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式