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1. 发明申请

US20180267128A1 Scanning Ferromagnetic Resonance (FMR) for Wafer-Level Characterization of Magnetic Films and Multilayers 审中-公开
公开(公告)号：US20180267128A1
公开(公告)日：2018-09-20
申请号：US15463074
申请日：2017-03-20
申请人： Headway Technologies, Inc.
发明人： Santiago Serrano Guisan , Luc Thomas , Son Le , Guenole Jan
IPC分类号： G01R33/60 , G01R33/345
CPC分类号： G01R33/60 , G01N24/10 , G01R31/318511 , G01R33/30 , G01R33/345 , H01L43/08 , H01L43/10 , H01P5/18
摘要： A ferromagnetic resonance (FMR) measurement system is disclosed with a waveguide transmission line (WGTL) connected at both ends to a mounting plate having an opening through which the WGTL is suspended. While the WGTL bottom surface contacts a portion of magnetic film on a whole wafer, a plurality of microwave frequencies is sequentially transmitted through the WGTL. Simultaneously, a magnetic field is applied to the contacted region thereby causing a FMR condition in the magnetic film. After RF output is transmitted through or reflected from the WGTL to a RF detector and converted to a voltage signal, effective anisotropy field, linewidth, damping coefficient, and/or inhomogeneous broadening are determined based on magnetic field intensity, microwave frequency and voltage output. A plurality of measurements is performed by controllably moving the WGTL or wafer and repeating the simultaneous application of microwave frequencies and magnetic field at additional preprogrammed locations on the magnetic film.

2. 发明授权

US09689923B2 Adaptive electrical testing of wafers 有权
公开(公告)号：US09689923B2
公开(公告)日：2017-06-27
申请号：US14450027
申请日：2014-08-01
申请人： KLA-Tencor Corporation
发明人： Sagar A. Kekare
IPC分类号： G06F17/50 , G01R31/3185 , H01L21/66
CPC分类号： G01R31/318511 , H01L22/14 , H01L22/20
摘要： A method and a system for determining one or more parameters for electrical testing of a wafer are provided. One method includes determining electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the electrical test paths. The method also includes determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the electrical test paths. In addition, the method includes acquiring information for one or more characteristics of a physical version of the wafer. The information is generated by performing an inline process on the physical version of the wafer. The method further includes altering at least one of the one or more parameters of the electrical testing for the wafer based on the acquired information.

3. 发明申请

US20160306007A1 ELECTRIC FIELD SENSOR, SYSTEM, AND METHOD FOR PROGRAMMING ELECTRONIC DEVICES ON A WAFER 有权
标题翻译：用于在WAFER上编程电子设备的电场传感器，系统和方法
公开(公告)号：US20160306007A1
公开(公告)日：2016-10-20
申请号：US14850432
申请日：2015-09-10
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： LIANJUN LIU , PHILIPPE BERNARD ROLAND LANCE , DAVID JOSEPH MONK , BABAK A. TAHERI
IPC分类号： G01R31/28 , G01R29/12 , G01R1/073
CPC分类号： G01R31/2884 , G01R31/3025 , G01R31/318511
摘要： An electric field sensor includes sense and reference cells. The sense cell produces a resistance that varies relative to an intensity of an electric field, and the reference cell produces a resistance that is invariable relative to the intensity of the electric field. An output signal indicative of the intensity of the electric field is determined using the difference between the resistances. A system includes an electric field source that outputs a digital test program as an electric field signal. The system further includes the electric field sensor formed with IC dies on a wafer. The electric field sensor receives the electric field signal. The received electric field signal is converted to the test program, and the test program is stored in memory on the wafer. The electric field source does not physically contact the dies, but can flood an entire surface of the wafer with the electric field signal.
摘要翻译：电场传感器包括有源和参考单元。感测单元产生相对于电场强度变化的电阻，并且参考单元产生相对于电场强度不变的电阻。使用电阻之间的差来确定表示电场强度的输出信号。系统包括输出作为电场信号的数字测试程序的电场源。该系统还包括在晶片上形成有IC管芯的电场传感器。电场传感器接收电场信号。接收的电场信号被转换为测试程序，测试程序存储在晶片上的存储器中。电场源不与裸片物理接触，而是可以用电场信号来淹没晶片的整个表面。

4. 发明申请

US20160259002A1 TESTER FOR INTEGRATED CIRCUITS ON A SILICON WAFER AND INTEGRATED CIRCUIT 审中-公开
标题翻译：硅集成电路集成电路测试仪
公开(公告)号：US20160259002A1
公开(公告)日：2016-09-08
申请号：US15057662
申请日：2016-03-01
申请人： STARCHIP
发明人： Cyrille LAMBERT , Sébastien BAYON , Alexandre CROGUENNEC
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/318511 , G01R31/31908
摘要： A tester for integrated circuits on a silicon wafer may include an input/output connection for testing an integrated circuit and circuitry causing the tester to perform: transferring a data frame to the integrated circuit via the input/output connection, the data frame including a time reference for the data included in the data frame, a field for validating the time reference and a data field including at least one integrated-circuit test command; and receiving a data frame via the input/output connection, the data in the data frame received having a duration that is a multiple of the time reference.
摘要翻译：用于硅晶片上的集成电路的测试器可以包括用于测试集成电路的输入/输出连接和导致测试者执行的电路：经由输入/输出连接将数据帧传送到集成电路，数据帧包括时间包括在数据帧中的数据的参考，用于验证时间参考的字段和包括至少一个集成电路测试命令的数据字段; 并且经由输入/输出连接接收数据帧，接收到的数据帧中的数据具有时间参考的倍数的持续时间。

5. 发明授权

US09417283B2 Semiconductor test system and method 有权
公开(公告)号：US09417283B2
公开(公告)日：2016-08-16
申请号：US14944903
申请日：2015-11-18
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/26 , G01R31/3177 , G06F11/26 , G01R31/3185 , G06F11/277 , G01R31/317 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318566 , G01R31/318572 , G01R31/31926 , G01R31/31932 , G06F11/26 , G06F11/277
摘要： A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

6. 发明授权

US09304164B2 Method and apparatus for RFID tag testing 有权
标题翻译： RFID标签测试方法和装置
公开(公告)号：US09304164B2
公开(公告)日：2016-04-05
申请号：US13655047
申请日：2012-10-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsiung Li , Kuang-Kai Yen , Yi-Hsuan Liu , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： G01R1/067 , G01R31/20 , G06K7/10 , G01R31/302 , G01R31/3185
CPC分类号： G01R1/06711 , G01R31/2607 , G01R31/28 , G01R31/3025 , G01R31/318511
摘要： A semiconductor wafer includes a plurality of dies and at least one test probe. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit. The at least one test probe includes a plurality of probe pads. The plurality of probe pads is configured to transmit power signals and data to each of the plurality of dies, and to receive test results from each of the plurality of dies. The data are transmitted to each of the plurality of dies in a serial manner. The test results of each of the plurality of dies are also transmitted to the plurality of probe pads in a serial manner.
摘要翻译：半导体晶片包括多个管芯和至少一个测试探针。多个管芯中的每一个都包括射频识别（RFID）标签电路。所述至少一个测试探针包括多个探针垫。多个探针焊盘被配置为将功率信号和数据传送到多个管芯中的每一个，并且从多个管芯中的每一个接收测试结果。以串行方式将数据发送到多个管芯中的每一个。多个管芯中的每一个的测试结果也以串行方式传输到多个探针焊盘。

7. 发明申请

US20160061887A1 WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE 审中-公开
标题翻译：使用2信号JTAG接口进行测距
公开(公告)号：US20160061887A1
公开(公告)日：2016-03-03
申请号：US14934451
申请日：2015-11-06
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
摘要翻译：晶片上晶片的测试是通过以下方式实现的：（1）向测试人员提供使用同时双向收发器电路外部传送JTAG测试信号的能力;（2）使用同时双向收发器电路在晶片上提供外部传送JTAG测试信号的能力，以及（3）提供连接测试器的双向收发器电路与晶片上所选择的组或晶片上的所有芯片之间的机制，用于通信JTAG信号。

8. 发明授权

US09207280B2 First/second die, channel interfaces, TAPs, and TLMs with common clock 有权
标题翻译：第一/第二芯片，通道接口，TAP和具有公共时钟的TLM
公开(公告)号：US09207280B2
公开(公告)日：2015-12-08
申请号：US14446873
申请日：2014-07-30
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
摘要翻译：晶片上晶片的测试是通过以下方式实现的：（1）向测试人员提供使用同时双向收发器电路外部传送JTAG测试信号的能力;（2）使用同时双向收发器电路在晶片上提供外部传送JTAG测试信号的能力，以及（3）提供连接测试器的双向收发器电路与晶片上所选择的组或晶片上的所有芯片之间的机制，用于通信JTAG信号。

9. 发明授权

US09121906B2 Semiconductor test system and method 有权
公开(公告)号：US09121906B2
公开(公告)日：2015-09-01
申请号：US14637098
申请日：2015-03-03
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/26 , G01R31/3177 , G01R31/3185 , G01R31/317 , G06F11/26 , G06F11/277 , G01R31/3193 , G01R31/319
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318566 , G01R31/318572 , G01R31/31926 , G01R31/31932 , G06F11/26 , G06F11/277
摘要： A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

10. 发明授权

US09103884B2 De-embedding on-wafer devices 有权
标题翻译：去嵌入晶圆器件
公开(公告)号：US09103884B2
公开(公告)日：2015-08-11
申请号：US12963511
申请日：2010-12-08
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Sa-Lly Liu
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Sa-Lly Liu
IPC分类号： G01R31/26 , G01R31/3185 , G11C29/56 , H01L21/66
CPC分类号： G01R31/2601 , G01R1/0491 , G01R31/2644 , G01R31/318511 , G11C29/56 , G11C2029/5602 , H01L22/34
摘要： A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.
摘要翻译：提供传输线。在一个实施例中，传输线包括衬底，衬底内的阱，阱上的屏蔽层以及屏蔽层上的多个中间金属层，多个中间金属层通过多个通孔耦合。传输线还包括多个中间金属层上的顶部金属层。还公开了用于去嵌入晶片装置和晶片的测试结构。

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