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1. 发明授权

US09996011B2 System and method for lithography alignment 有权
公开(公告)号：US09996011B2
公开(公告)日：2018-06-12
申请号：US15090108
申请日：2016-04-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Hsien Lin , Hung-Chang Hsieh , Feng-Jia Shiu , Chun-Yi Lee
IPC分类号： G03B27/42 , G03B27/54 , G03B27/32 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70141 , G03F9/7084
摘要： A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.

2. 发明授权

US11955547B2 Semiconductor device including an epitaxy region 有权
公开(公告)号：US11955547B2
公开(公告)日：2024-04-09
申请号：US16227107
申请日：2018-12-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Te-Jen Pan , Yu-Hsien Lin , Hsiang-Ku Shen , Wei-Han Fan , Yun Jing Lin , Yimin Huang , Tzu-Chung Wang
IPC分类号： H01L29/78 , H01L21/8238 , H01L29/04 , H01L29/06 , H01L29/165 , H01L29/66
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L29/04 , H01L29/0649 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

3. 发明授权

US10522413B2 Method of forming source/drain contact 有权
公开(公告)号：US10522413B2
公开(公告)日：2019-12-31
申请号：US16229260
申请日：2018-12-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming-Jhih Kuo , Yu-Hsien Lin , Hung-Chang Hsieh , Jhun Hua Chen
IPC分类号： H01L21/8234 , H01L21/311 , H01L27/088 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/768 , H01L29/165
摘要： Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.

4. 发明申请

US20190131298A1 Semiconductor Structure Cutting Process and Structures Formed Thereby 审中-公开
公开(公告)号：US20190131298A1
公开(公告)日：2019-05-02
申请号：US16205422
申请日：2018-11-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ryan Chia-Jen Chen , Cheng-Chung Chang , Shao-Hua Hsu , Yu-Hsien Lin , Ming-Ching Chang , Li-Wei Yin , Tzu-Wen Pan , Yi-Chun Chen
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/3065 , H01L27/02 , H01L29/66 , H01L21/762 , H01L21/3213 , H01L29/78 , H01L29/06
摘要： Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

5. 发明授权

US10164093B2 Semiconductor device including an epitaxy region 有权
公开(公告)号：US10164093B2
公开(公告)日：2018-12-25
申请号：US15457613
申请日：2017-03-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Te-Jen Pan , Yu-Hsien Lin , Hsiang-Ku Shen , Wei-Han Fan , Yun Jing Lin , Yimin Huang , Tzu-Chung Wang
IPC分类号： H01L29/76 , H01L29/78 , H01L21/8238 , H01L29/165 , H01L29/66 , H01L29/04 , H01L29/06
摘要： An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.

6. 发明公开

US20240120388A1 TUNABLE STRUCTURE PROFILE 审中-公开
公开(公告)号：US20240120388A1
公开(公告)日：2024-04-11
申请号：US18155933
申请日：2023-01-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Li-Wei Yin , Tzu-Wen Pan , Yu-Hsien Lin , Jih-Sheng Yang , Shih-Chieh Chao , Chia Ming Liang , Yih-Ann Lin , Ryan Chia-Jen Chen
IPC分类号： H01L29/40 , H01L21/3213 , H01L29/423
CPC分类号： H01L29/401 , H01L21/32139 , H01L29/42376
摘要： Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

7. 发明公开

US20240105795A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 审中-公开
公开(公告)号：US20240105795A1
公开(公告)日：2024-03-28
申请号：US18170387
申请日：2023-02-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jun-Ye Liu , Jih-Sheng Yang , Yu-Hsien Lin , Ryan Chia-Jen Chen
IPC分类号： H01L29/423 , H01L21/28 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L29/42376 , H01L21/28088 , H01L21/28114 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.

8. 发明公开

US20240072170A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 审中-公开
公开(公告)号：US20240072170A1
公开(公告)日：2024-02-29
申请号：US17894614
申请日：2022-08-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Li-Wei Yin , Tzu-Wen Pan , Yu-Hsien Lin , Yu-Shih Wang , Yih-Ann Lin , Chia Ming Liang , Ryan Chia-Jen CHEN
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7851 , H01L29/66545 , H01L29/6656 , H01L29/66795
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

9. 发明申请

US20160216613A1 SYSTEM AND METHOD FOR LITHOGRAPHY ALIGNMENT 有权
标题翻译：系统和方法的LITHOGRAPHY对齐
公开(公告)号：US20160216613A1
公开(公告)日：2016-07-28
申请号：US15090108
申请日：2016-04-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Hsien Lin , Hung-Chang Hsieh , Feng-Jia Shiu , Chun-Yi Lee
IPC分类号： G03F7/20
CPC分类号： G03F7/70141 , G03F9/7084
摘要： A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.
摘要翻译：一种方法提供了具有限定在第一图案层中的第一和第二对准标记的集成电路（IC）基板，以及限定在第二图案层中的第三和第四对准标记。第一和第二对准标记通过光掩模用第一光照亮，以确定包括第一对准误差和第二对准误差的第一层对准误差。在确定第一层对准误差时，第一对准误差比第二对准误差具有更多的权重。用第二光照射第三和第四对准标记，以确定包括相对于第三对准标记的第三对准误差和与第四对准标记相关的第四对准误差的第二层对准误差。在确定第二层对准误差时，第三对准误差比第四对准误差具有更多的权重。

10. 发明授权

US09304403B2 System and method for lithography alignment 有权
标题翻译：光刻对准的系统和方法
公开(公告)号：US09304403B2
公开(公告)日：2016-04-05
申请号：US13732913
申请日：2013-01-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Hsien Lin , Hung-Chang Hsieh , Feng-Jia Shiu , Chun-Yi Lee
IPC分类号： G03B27/42 , G03B27/54 , G03B27/32 , G03F7/20 , G03F9/00 , G03B27/58
CPC分类号： G03F7/70141 , G03F9/7084
摘要： The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate.
摘要翻译：本公开提供了用于集成电路制造的光刻系统的一个实施例。该系统包括设计成固定基板并可操作以移动基板的基板台; 对准模块，其包括可调谐光源，其可操作以产生具有波长可调谐的红外光; 和接收光的检测器; 以及与所述对准模块集成并被设计为对涂覆在所述基板上的抗蚀剂层进行曝光处理的曝光模块。

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