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1. 发明授权

US09589095B2 Method of converting between non-volatile memory technologies and system for implementing the method 有权
标题翻译：在非易失性存储器技术之间转换的方法和用于实现该方法的系统
公开(公告)号：US09589095B2
公开(公告)日：2017-03-07
申请号：US14878039
申请日：2015-10-08
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hung-Cheng Sung , Yue-Der Chih , Chia-Hsing Chen
IPC分类号： G06F17/50 , H01L29/788 , H01L29/792 , H01L29/66 , H01L27/02 , H01L27/115
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5077 , G06F2217/06 , G06F2217/78 , H01L27/0207 , H01L27/11531 , H01L27/11573 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of designing a charge trapping memory array includes designing a memory array layout. The memory array layout includes a first type of transistors; electrical connections between memory cells of the memory array layout; a first input/output (I/O) interface; and a charge pump. The method further includes modifying the memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes modifying the memory array layout, using the processor, to modify the charge pump based on an operating voltage of the second type of transistors.
摘要翻译：设计电荷俘获存储器阵列的方法包括设计存储器阵列布局。存储器阵列布局包括第一类型的晶体管; 存储器阵列布局的存储单元之间的电连接; 第一个输入/输出（I / O）接口; 和电荷泵。该方法还包括使用处理器来修改存储器阵列布局，以用与第一类型的晶体管不同的第二类型的晶体管代替第一类型的晶体管。该方法还包括使用处理器修改存储器阵列布局，以基于第二类型晶体管的工作电压修改电荷泵。

2. 发明授权

US09190995B2 Multiple power domain electronic device and related method 有权
公开(公告)号：US09190995B2
公开(公告)日：2015-11-17
申请号：US14547628
申请日：2014-11-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jerry Chen , Hsu-Shun Chen , Gu-Huan Li , Cheng-Hsiung Kuo , Yue-Der Chih
IPC分类号： H03L7/00 , H03K17/22 , G06F1/24
CPC分类号： H03K17/223 , G06F1/24 , G06F1/26
摘要： An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.

3. 发明申请

US20150063048A1 Sample-and-Hold Current Sense Amplifier and Related Method 有权
标题翻译：采样保持电流检测放大器及相关方法
公开(公告)号：US20150063048A1
公开(公告)日：2015-03-05
申请号：US14016917
申请日：2013-09-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ku-Feng Lin , Hung-Chang Yu , Yue-Der Chih
IPC分类号： H03F3/45 , G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C7/08 , G11C27/02 , G11C2207/063
摘要： A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.
摘要翻译：器件包括放大器和第一开关电流采样器。第一开关电流采样器包括第一晶体管，第一电容器以及第一，第二和第三开关。第一电容器具有电连接到第一晶体管的栅电极的第一端子和与第一晶体管的源电极电连接的第二端子。第一开关具有电连接到第一电流源的第一端子和电连接到第一晶体管的栅电极的第二端子。第二开关具有电连接到第一电流源的第一端子和与第一晶体管的漏电极电连接的第二端子。第三开关具有电连接到第一晶体管的漏电极的第一端子和与放大器的第一输入端子电连接的第二端子。

4. 发明授权

US10141063B2 Memory controller, memory device and method of operating 有权
公开(公告)号：US10141063B2
公开(公告)日：2018-11-27
申请号：US14075097
申请日：2013-11-08
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yue-Der Chih , Cheng-Hsiung Kuo , Gu-Huan Li
IPC分类号： G11C16/34 , G11C16/14 , G11C16/24
摘要： A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell.

5. 发明申请

US20160197060A1 PACKAGE WITH MULTIPLE PLANE I/O STRUCTURE 审中-公开
公开(公告)号：US20160197060A1
公开(公告)日：2016-07-07
申请号：US15071920
申请日：2016-03-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Chang Yu , Kai-Chun Lin , Yue-Der Chih
IPC分类号： H01L25/065 , H01L23/498 , H01L23/00 , H01L25/00 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/56 , H01L21/565 , H01L23/3107 , H01L23/3128 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/065 , H01L25/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05554 , H01L2224/06181 , H01L2224/09181 , H01L2224/131 , H01L2224/16055 , H01L2224/16057 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1712 , H01L2224/17179 , H01L2224/17181 , H01L2224/75702 , H01L2224/81191 , H01L2224/81801 , H01L2224/81815 , H01L2224/9202 , H01L2225/06517 , H01L2225/06582 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2224/11 , H01L2924/014
摘要： A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.

6. 发明授权

US09299677B2 Package with multiple plane I/O structure 有权
标题翻译：具有多个平面I / O结构的封装
公开(公告)号：US09299677B2
公开(公告)日：2016-03-29
申请号：US14144813
申请日：2013-12-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Chang Yu , Kai-Chun Lin , Yue-Der Chih
IPC分类号： H01L29/80 , H01L23/00 , H01L23/498 , H01L21/56 , H01L23/31 , H01L25/065
CPC分类号： H01L25/0657 , H01L21/56 , H01L21/565 , H01L23/3107 , H01L23/3128 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/065 , H01L25/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05554 , H01L2224/06181 , H01L2224/09181 , H01L2224/131 , H01L2224/16055 , H01L2224/16057 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1712 , H01L2224/17179 , H01L2224/17181 , H01L2224/75702 , H01L2224/81191 , H01L2224/81801 , H01L2224/81815 , H01L2224/9202 , H01L2225/06517 , H01L2225/06582 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2224/11 , H01L2924/014
摘要： A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.
摘要翻译：实施例包装包括三维集成电路（3D IC），其具有第一侧上的第一输入/输出焊盘和第二侧上的第二输入/输出焊盘，电耦合到第二侧上的第一输入/输出焊盘的第一扇出结构三维集成电路的第一侧，以及电耦合到三维集成电路的第二侧上的第二输入/输出焊盘的第二扇出结构。

7. 发明授权

US09183895B2 Memory with dynamic feedback control circuit 有权
标题翻译：内存带动态反馈控制电路
公开(公告)号：US09183895B2
公开(公告)日：2015-11-10
申请号：US14446573
申请日：2014-07-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hung-Chang Yu , Yue-Der Chih
IPC分类号： G11C7/06 , G11C5/14 , G11C8/08 , G11C7/10 , G11C7/12
CPC分类号： G11C5/145 , G11C5/147 , G11C7/12 , G11C8/08
摘要： A memory comprising a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is configured to boost the word line voltage to a predetermined voltage value greater than a target threshold voltage, change a clock frequency of a clock signal supplied to the charge pump from a non-zero frequency to a zero frequency if the word line voltage is above the predetermined voltage value, and change the clock frequency from the zero frequency to the non-zero frequency if the word line voltage is below the target threshold voltage.
摘要翻译：包括具有字线电压的字线，耦合到字线的电荷泵和耦合到电荷泵的动态反馈控制电路的存储器。动态反馈控制电路被配置为将字线电压升高到大于目标阈值电压的预定电压值，将提供给电荷泵的时钟信号的时钟频率从非零频率改变为零频率，如果字线电压高于预定电压值，如果字线电压低于目标阈值电压，则将时钟频率从零频率改变为非零频率。

8. 发明授权

US09165613B2 Sample-and-hold current sense amplifier and related method 有权
标题翻译：采样保持电流检测放大器及相关方法
公开(公告)号：US09165613B2
公开(公告)日：2015-10-20
申请号：US14016917
申请日：2013-09-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ku-Feng Lin , Hung-Chang Yu , Yue-Der Chih
IPC分类号： G11C7/02 , G11C7/06 , G11C7/08
CPC分类号： G11C7/062 , G11C7/067 , G11C7/08 , G11C27/02 , G11C2207/063
摘要： A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.
摘要翻译：器件包括放大器和第一开关电流采样器。第一开关电流采样器包括第一晶体管，第一电容器以及第一，第二和第三开关。第一电容器具有电连接到第一晶体管的栅电极的第一端子和与第一晶体管的源电极电连接的第二端子。第一开关具有电连接到第一电流源的第一端子和电连接到第一晶体管的栅电极的第二端子。第二开关具有电连接到第一电流源的第一端子和与第一晶体管的漏电极电连接的第二端子。第三开关具有电连接到第一晶体管的漏电极的第一端子和与放大器的第一输入端子电连接的第二端子。

9. 发明授权

US08929137B2 Operating method of memory having redundancy circuitry 有权
标题翻译：具有冗余电路的存储器的操作方法
公开(公告)号：US08929137B2
公开(公告)日：2015-01-06
申请号：US14168257
申请日：2014-01-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tien-Chun Yang , Yue-Der Chih , Shang-Hsuan Liu
IPC分类号： G11C11/34 , G11C29/04 , G11C16/04 , G11C29/00
CPC分类号： G11C29/04 , G11C16/0408 , G11C16/0483 , G11C29/808
摘要： In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.
摘要翻译：在一种操作存储器电路的方法中，存储器电路包括多个存储器阵列，每个存储器阵列与相应的输入/输出（IO）接口和冗余存储器页面耦合，确定故障位单元的故障地址。故障地址位于其中一个存储器阵列的存储器页面中。该方法还包括通过用冗余存储器页替换存储器页来修复故障位单元。

10. 发明授权

US08928372B2 Multiple power domain electronic device and related method 有权
标题翻译：多功率域电子设备及相关方法
公开(公告)号：US08928372B2
公开(公告)日：2015-01-06
申请号：US13791155
申请日：2013-03-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jerry Chen , Hsu-Shun Chen , Gu-Huan Li , Cheng-Hsiung Kuo , Yue-Der Chih
IPC分类号： H03L7/00 , H03K17/22
CPC分类号： H03K17/223 , G06F1/24 , G06F1/26
摘要： An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.
摘要翻译：电子设备包括第一电路，第二电路和上电控制（POC）电路。 POC电路包括电连接到第一电路的第一输出的使能端子，电连接到第一电压源的第一输入端子，电连接到第二电压源的第二输入端子和输出端子。第二电路包括偏置敏感电路，以及包括电连接到第一电路的第二输出的第一输入端的逻辑电路，电连接到POC电路的输出的第二输入端和电连接的输出端到偏置敏感电路的使能端子。

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