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1. 发明授权

US10699964B2 Silicon and silicon germanium nanowire formation 有权
公开(公告)号：US10699964B2
公开(公告)日：2020-06-30
申请号：US16205419
申请日：2018-11-30
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Kuo-Cheng Ching , Carlos H. Diaz , Jean-Pierre Colinge
IPC分类号： H01L21/8238 , H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/66 , H01L29/786 , H01L29/423 , H01L29/775 , H01L29/06 , H01L27/092 , H01L29/16
摘要： Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

2. 发明授权

US10290737B2 Semiconductor arrangement with one or more semiconductor columns 有权
公开(公告)号：US10290737B2
公开(公告)日：2019-05-14
申请号：US15983444
申请日：2018-05-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Jean-Pierre Colinge , Kuo-Cheng Ching , Ta-Pen Guo , Carlos H. Diaz
IPC分类号： H01L21/308 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/66 , B82Y10/00 , B82Y40/00 , H01L29/775 , H01L21/3213
摘要： A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.

3. 发明授权

US09911812B2 Semiconductor device having a fin shell covering a fin core 有权
公开(公告)号：US09911812B2
公开(公告)日：2018-03-06
申请号：US14937327
申请日：2015-11-10
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Chun-Hsiung Lin , Carlos H. Diaz , Hui-Cheng Chang , Syun-Ming Jang , Mao-Lin Huang , Chien-Hsun Wang
IPC分类号： H01L29/205 , H01L29/06 , H01L29/78 , H01L29/267 , H01L29/10 , H01L21/762
CPC分类号： H01L29/205 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1054 , H01L29/267 , H01L29/785 , H01L29/7853
摘要： According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.

4. 发明授权

US09881993B2 Method of forming semiconductor structure with horizontal gate all around structure 有权
公开(公告)号：US09881993B2
公开(公告)日：2018-01-30
申请号：US14317069
申请日：2014-06-27
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Kuo-Cheng Ching , Ching-Wei Tsai , Chih-Hao Wang , Carlos H. Diaz
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66 , H01L29/423 , H01L29/10 , H01L29/167 , H01L21/762 , H01L21/8234 , H01L29/267
CPC分类号： H01L29/0615 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823481 , H01L29/0673 , H01L29/1054 , H01L29/167 , H01L29/267 , H01L29/42392 , H01L29/66795 , H01L29/785
摘要： A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material. The plurality of channel layers includes a top channel layer above a bottom channel layer. Each channel layer comprises a first sublayer of removable semiconductor material overlaid by a second sublayer of semiconductor material. The method further comprises providing shallow trench isolation (STI) material between the vertical slices of the bulk substrate in the plurality of fins, depositing poly material around a central portion of the plurality of fins, forming source and drain regions, and forming an interlayer dielectric layer (ILD0). The method also comprises removing the poly material, forming a plurality of channels from the channel layers, and forming a gate around the channels.

5. 发明授权

US09764950B2 Semiconductor arrangement with one or more semiconductor columns 有权
公开(公告)号：US09764950B2
公开(公告)日：2017-09-19
申请号：US14287155
申请日：2014-05-26
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Ta-Pen Guo , Chih-Hao Wang , Carlos H. Diaz
IPC分类号： H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/66 , H01L29/775 , H01L29/06 , H01L21/308 , H01L29/423
CPC分类号： B82Y10/00 , B82Y40/00 , H01L29/0676 , H01L29/42392 , H01L29/66439 , H01L29/775
摘要： A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.

6. 发明授权

US09735146B2 Vertical nanowire transistor for input/output structure 有权
公开(公告)号：US09735146B2
公开(公告)日：2017-08-15
申请号：US14923493
申请日：2015-10-27
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Ta-Pen Guo , Carlos H. Diaz
IPC分类号： H01L29/78 , H01L27/02 , H01L23/60
CPC分类号： H01L27/0266 , H01L23/60 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region.

7. 发明申请

US20170117377A1 Semiconductor Structures and Methods for Multi-Level Work Function 审中-公开
公开(公告)号：US20170117377A1
公开(公告)日：2017-04-27
申请号：US15401171
申请日：2017-01-09
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Chia-Wen Liu , Wei-Hao Wu , Chih-Hao Wang , Carlos H. Diaz
IPC分类号： H01L29/49 , H01L29/66 , H01L29/786 , H01L27/092 , H01L29/06 , H01L29/423
CPC分类号： H01L29/4908 , H01L21/28008 , H01L21/823412 , H01L21/823437 , H01L21/823462 , H01L21/823487 , H01L21/845 , H01L27/088 , H01L27/092 , H01L29/0676 , H01L29/41 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/42392 , H01L29/4983 , H01L29/66439 , H01L29/66666 , H01L29/66742 , H01L29/775 , H01L29/7788 , H01L29/7827 , H01L29/78642 , H01L2029/42388
摘要： Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a drain region. A first metal gate surrounds a portion of the vertical channel structure and has a gate length. The first metal gate has a first gate section with a first workfunction and a first thickness. The first metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness is different from the second thickness, and the sum of the first thickness and the second thickness is equal to the gate length. A ratio of the first thickness to the second thickness is chosen to achieve a desired threshold voltage level for the semiconductor device.

8. 发明授权

US09570579B2 Semiconductor structures and methods for multi-level work function 有权
标题翻译：半导体结构和多级功能的方法
公开(公告)号：US09570579B2
公开(公告)日：2017-02-14
申请号：US14852679
申请日：2015-09-14
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Carlos H. Diaz
IPC分类号： H01L29/66 , H01L29/78 , H01L29/49 , H01L29/43 , H01L21/28 , H01L29/423 , H01L29/40 , H01L29/775 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28088 , H01L29/0676 , H01L29/1045 , H01L29/401 , H01L29/4232 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/4983 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/7827
摘要： Semiconductor devices that each include a channel region and a gate stack are disclosed. The gate stack includes a gate insulator, a pair of spaced apart first metal gate layers, and a second metal gate layer. The gate insulator extends along the length of the channel region. The first metal gate layers have a first workfunction and extend from the gate insulator. The second metal gate layer is disposed between the first metal gate layers, has a second workfunction different from the first workfunction, and extends from the gate insulator. Methods of fabricating the gate stack are also disclosed.
摘要翻译：公开了各自包括沟道区和栅叠层的半导体器件。栅极堆叠包括栅极绝缘体，一对间隔开的第一金属栅极层和第二金属栅极层。栅极绝缘体沿着沟道区域的长度延伸。第一金属栅层具有第一功函数并从栅极绝缘体延伸。第二金属栅极层设置在第一金属栅极层之间，具有与第一功函数不同的第二功函，并从栅极绝缘体延伸。还公开了制造栅叠层的方法。

9. 发明授权

US09177924B2 Vertical nanowire transistor for input/output structure 有权
标题翻译：用于输入/输出结构的垂直纳米线晶体管
公开(公告)号：US09177924B2
公开(公告)日：2015-11-03
申请号：US14132076
申请日：2013-12-18
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Ta-Pen Guo , Carlos H. Diaz
IPC分类号： H01L23/60
CPC分类号： H01L27/0266 , H01L23/60 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： Systems for protecting a circuit from an electrostatic discharge (ESD) voltage are provided. An input terminal receives an input signal. An ESD protection circuit receives the input signal from the input terminal. The ESD protection circuit includes one or more vertical nanowire field effect transistors (FETs). Each of the one or more vertical nanowire FETs includes a well of a first conductivity type. Each of the one or more vertical nanowire FETs also includes a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire that is opposite the first end. The source region further includes a portion formed in the well, where the source region and the drain region are of a second conductivity type. A gate region surrounds a portion of the nanowire and is separated from the drain region by a distance.
摘要翻译：提供了用于保护电路免受静电放电（ESD）电压的系统。输入端接收输入信号。 ESD保护电路从输入端接收输入信号。 ESD保护电路包括一个或多个垂直纳米线场效应晶体管（FET）。一个或多个垂直纳米线FET中的每一个包括第一导电类型的阱。一个或多个垂直纳米线FET中的每一个还包括具有i）在纳米线的第一端处的源极区域和ii）在纳米线的与第一端相对的第二端处的漏极区域的纳米线。源极区还包括形成在阱中的部分，其中源区和漏区是第二导电类型。栅极区域围绕纳米线的一部分并且与漏极区域分开一段距离。

10. 发明申请

US20150200300A1 SEMICONDUCTOR DEVICE AND FORMATION THEREOF 有权
标题翻译：半导体器件及其形成
公开(公告)号：US20150200300A1
公开(公告)日：2015-07-16
申请号：US14155793
申请日：2014-01-15
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Kuo-Cheng Ching , Chih-Hao Wang , Zhiqiang Wu , Carlos H. Diaz
IPC分类号： H01L29/78 , H01L21/02 , H01L29/16 , H01L29/06 , H01L29/66 , H01L21/762
CPC分类号： H01L29/7851 , H01L21/02164 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/76224 , H01L21/76235 , H01L29/0638 , H01L29/0649 , H01L29/16 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow.
摘要翻译：本文提供半导体器件和形成方法。半导体器件包括具有沿着第一平面延伸的第一壁的鳍片，鳍片包括在第一平面的第一侧上限定第一沟槽的掺杂区域。电介质设置在第一沟槽内，使得电介质与电介质的第一端和电介质的第二端之间的第一沟槽接触。第一端与第一平面分开第一距离。与包括不包括设置在沟槽内的电介质的翅片的FinFet相比，设置在沟槽内的电介质增加了相邻散热片的通道部分的隔离，从而减小了FinFet的漏电流。

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