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1. 发明授权

US09343140B2 Boosted read write word line 有权
公开(公告)号：US09343140B2
公开(公告)日：2016-05-17
申请号：US14844215
申请日：2015-09-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Yen-Huei Chen , Chih-Yu Lin , Li-Wen Wang , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/00 , G11C11/419 , G11C8/16 , G11C8/08 , G11C11/418
CPC分类号： G11C11/419 , G11C8/08 , G11C8/16 , G11C11/418
摘要： One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.

2. 发明申请

US20150380082A1 BOOSTED READ WRITE WORD LINE 有权
标题翻译：增强阅读写字线
公开(公告)号：US20150380082A1
公开(公告)日：2015-12-31
申请号：US14844215
申请日：2015-09-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Yen-Huei Chen , Chih-Yu Lin , Li-Wen Wang , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C8/08 , G11C8/16 , G11C11/418
摘要： One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.
摘要翻译：本文提供了用于升高两端口同步随机存取存储器（SRAM）位单元阵列的读字线（RWL）或写字线（WWL）的一种或多种技术或系统。在一些实施例中，升压控制块被配置为产生被配置为操作RWL，WWL或读写字线（RWWL）的升压字线信号。在一些实施例中，升压的字线信号包括第一级和第二级。例如，第一级与正电源电压（Vdd）电压电平处的第一级电压电平相关联，并且第二级与高于Vdd电压电平的第二级电压电平相关联。以这种方式，对于SRAM位单元，升压读或写操作，因为例如，第二级升高SRAM位单元中的相应晶体管。

3. 发明申请

US20210050053A1 Low Voltage Bit-Cell 有权
公开(公告)号：US20210050053A1
公开(公告)日：2021-02-18
申请号：US17087711
申请日：2020-11-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Mahmut Sinangil , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Yen-Ting Lin
IPC分类号： G11C11/419 , G11C5/14 , G11C8/16 , G11C7/10 , G11C11/413
摘要： Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.

4. 发明授权

US08923078B2 Voltage divider control circuit 有权
标题翻译：分压器控制电路
公开(公告)号：US08923078B2
公开(公告)日：2014-12-30
申请号：US13751240
申请日：2013-01-28
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Yangsyu Lin , Hsin-Hsin Ko , Chiting Cheng , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/00 , H03K17/284
CPC分类号： H03K17/284 , G11C7/00 , G11C11/417 , H03K17/04123
摘要： One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly.
摘要翻译：本文提供了用于控制分压器的一种或多种技术或系统。在一些实施例中，控制电路被配置为使用模拟信号来偏置分压器的上拉单元，从而使分压器能够可调。换句话说，控制电路使得分压器能够输出多个电压电平。另外，控制电路被配置为基于与分压器的下拉单元相关联的偏置定时偏压上拉单元。例如，下拉单元启动后，上拉单元被激活。以这种方式，控制电路提供定时提升，从而使得分压器能够更快地稳定。

5. 发明申请

US20140211574A1 VOLTAGE DIVIDER CONTROL CIRCUIT 有权
标题翻译：电压分压器控制电路
公开(公告)号：US20140211574A1
公开(公告)日：2014-07-31
申请号：US13751240
申请日：2013-01-28
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Yangsyu Lin , Hsin-Hsin Ko , Chiting Cheng , Jonathan Tsung-Yung Chang
IPC分类号： H03K17/284 , G11C7/00
CPC分类号： H03K17/284 , G11C7/00 , G11C11/417 , H03K17/04123
摘要： One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly.
摘要翻译：本文提供了用于控制分压器的一种或多种技术或系统。在一些实施例中，控制电路被配置为使用模拟信号来偏置分压器的上拉单元，从而使分压器能够可调。换句话说，控制电路使得分压器能够输出多个电压电平。另外，控制电路被配置为基于与分压器的下拉单元相关联的偏置定时偏压上拉单元。例如，下拉单元启动后，上拉单元被激活。以这种方式，控制电路提供定时提升，从而使得分压器能够更快地稳定。

6. 发明授权

US11200946B2 Low voltage bit-cell 有权
公开(公告)号：US11200946B2
公开(公告)日：2021-12-14
申请号：US17087711
申请日：2020-11-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Mahmut Sinangil , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Yen-Ting Lin
IPC分类号： G11C11/419 , G11C5/14 , G11C8/16 , G11C7/10 , G11C11/413
摘要： Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.

7. 发明授权

US09135971B2 Boosted read write word line 有权
标题翻译：增强读写字线
公开(公告)号：US09135971B2
公开(公告)日：2015-09-15
申请号：US13753731
申请日：2013-01-30
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Yen-Huei Chen , Chih-Yu Lin , Li-Wen Wang , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/00 , G11C8/16 , G11C8/08 , G11C11/418
CPC分类号： G11C11/419 , G11C8/08 , G11C8/16 , G11C11/418
摘要： One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.
摘要翻译：本文提供了用于升高两端口同步随机存取存储器（SRAM）位单元阵列的读字线（RWL）或写字线（WWL）的一种或多种技术或系统。在一些实施例中，升压控制块被配置为产生被配置为操作RWL，WWL或读写字线（RWWL）的升压字线信号。在一些实施例中，升压的字线信号包括第一级和第二级。例如，第一级与正电源电压（Vdd）电压电平处的第一级电压电平相关联，并且第二级与高于Vdd电压电平的第二级电压电平相关联。以这种方式，对于SRAM位单元，升压读或写操作，因为例如，第二级升高SRAM位单元中的相应晶体管。

8. 发明申请

US20140211578A1 BOOSTED READ WRITE WORD LINE 有权
标题翻译：增强阅读写字线
公开(公告)号：US20140211578A1
公开(公告)日：2014-07-31
申请号：US13753731
申请日：2013-01-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Yen-Huei Chen , Chih-Yu Lin , Li-Wen Wang , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G11C8/16 , G11C7/00
CPC分类号： G11C11/419 , G11C8/08 , G11C8/16 , G11C11/418
摘要： One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.
摘要翻译：本文提供了用于升高两端口同步随机存取存储器（SRAM）位单元阵列的读字线（RWL）或写字线（WWL）的一种或多种技术或系统。在一些实施例中，升压控制块被配置为产生被配置为操作RWL，WWL或读写字线（RWWL）的升压字线信号。在一些实施例中，升压的字线信号包括第一级和第二级。例如，第一级与正电源电压（Vdd）电压电平处的第一级电压电平相关联，并且第二级与高于Vdd电压电平的第二级电压电平相关联。以这种方式，对于SRAM位单元，升压读或写操作，因为例如，第二级升高SRAM位单元中的相应晶体管。

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