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1. 发明授权

US06642576B1 Power semiconductor device having layered structure of power semiconductor elements and terminal members 有权
标题翻译：功率半导体器件具有功率半导体元件和端子元件的分层结构
公开(公告)号：US06642576B1
公开(公告)日：2003-11-04
申请号：US10330438
申请日：2002-12-30
申请人： Takaaki Shirasawa , Yasuo Koutake , Tsuyoshi Takayama , Natsuki Tsuji
发明人： Takaaki Shirasawa , Yasuo Koutake , Tsuyoshi Takayama , Natsuki Tsuji
IPC分类号： H01L2976
CPC分类号： H01L25/071 , H01L25/18 , H01L2224/32225 , H01L2224/32245 , H01L2924/09701 , H01L2924/1305 , H01L2924/13055 , H01L2924/3011 , H01L2924/00
摘要： An IGBT (121) and a diode (131) are joined onto an element arrangement portion (111a) of a first terminal member (111) and an element arrangement portion (112a) of a second terminal member (112) is joined onto the IGBT (121) and the diode (131). Further, an IGBT (122) and a diode (132) are joined onto the element arrangement portion (112a) of the second terminal member (112) and an element arrangement portion (113a) of a third terminal member (113) is joined onto the IGBT (122) and the diode (132). A transfer mold package (141) is so formed as to house the elements (121, 122, 131, 132). External connection portions (111b, 112b, 113b) of the terminal members (111, 112, 113) are drawn out of the package (141). The element arrangement portion(s) (111a, 113a) of the first and/or third terminal member (111, 113) are/is exposed out of the package (141).
摘要翻译：将IGBT（121）和二极管（131）接合到第一端子部件（111）的元件配置部（111a）上，将第二端子部件（112）的元件配置部（112a）接合到IGBT （121）和二极管（131）。此外，IGBT（122）和二极管（132）接合到第二端子构件（112）的元件布置部分（112a）上，并且第三端子构件（113）的元件布置部分（113a）接合到 IGBT（122）和二极管（132）。传送模具包装141被形成为容纳元件121,122,131,132。端子构件（111,112,113）的外部连接部分（111b，112b，113b）从封装（141）中拉出。第一和/或第三端子构件（111,113）的元件排列部分（111a，113a）从包装（141）中露出。

2. 发明申请

US20090096502A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090096502A1
公开(公告)日：2009-04-16
申请号：US12116570
申请日：2008-05-07
申请人： Noboru MIYAMOTO , Natsuki Tsuji
发明人： Noboru MIYAMOTO , Natsuki Tsuji
IPC分类号： H03K17/28
CPC分类号： H02M1/38 , H02M2001/385 , H03K17/0828 , H03K17/165
摘要： The present invention provides a semiconductor device includes arms formed by two semiconductor elements, a map memory device which stores therein a correlation map between a control value for each of the arms and an optimized dead time to be set for the control value or is capable of storing the same therein, drive control value acquiring means for acquiring a drive control value of each of the arms, and a dead time generating circuit for extracting the optimized dead time corresponding to the drive control value from the correlation map. The time taken until the other of the semiconductor elements is turned on after one thereof has received a command to turn off the same is the optimized dead time extracted by the dead time generating circuit.
摘要翻译：本发明提供了一种半导体器件，包括由两个半导体元件形成的臂，地图存储器件，其中存储有用于每个臂的控制值与要设置的控制值的优化死区时间之间的相关图，或者能够存储其中的驱动控制值获取装置，用于获取每个臂的驱动控制值;以及死区时间生成电路，用于从相关图提取与驱动控制值相对应的优化死区时间。在其中一个半导体元件中的一个已经接收到关闭它的命令之后，其余的半导体元件所经过的时间是由死区时间产生电路提取的优化的死区时间。

3. 发明授权

US07101793B2 Power module and its manufacturing method 有权
标题翻译：电源模块及其制造方法
公开(公告)号：US07101793B2
公开(公告)日：2006-09-05
申请号：US11105562
申请日：2005-04-14
申请人： Natsuki Tsuji
发明人： Natsuki Tsuji
IPC分类号： H01L21/44
CPC分类号： H05K3/306 , H05K1/119 , H05K1/182 , H05K3/3405 , H05K3/403 , H05K2201/09163 , H05K2201/09181 , H05K2201/09827 , H05K2201/10053 , H05K2201/10446 , H05K2201/10568 , H05K2201/10863 , H05K2203/0195 , H05K2203/167
摘要： A method of manufacturing a power module is implemented which allows easy electrical connections between a control board and relay terminals. The diameter of through holes in the control board tapers down from a side of penetration of the relay terminals in a direction of the penetration, and respective one ends of the relay terminals have a smaller diameter than the other portions of the relay terminals. The diameter of the through holes on the side of penetration of the relay terminals is made sufficiently greater than the diameter of the one ends of the relay terminals, so that the relay terminals can easily penetrate the through holes. Further, even if the relay terminals are formed in deviated positions, the one ends of the relay terminals can be guided along the walls of the through holes in the penetration, so that the relay terminals can be adjusted to proper positions.
摘要翻译：实现制造电源模块的方法，其允许控制板和中继端子之间的容易的电连接。控制板上的通孔的直径从中继端子在穿透方向的穿透侧逐渐变细，并且继电器端子的相应一端具有比中继端子的其它部分更小的直径。继电器端子穿透侧的贯通孔的直径比继电器端子一端的直径大得多，使得继电器端子容易穿透通孔。此外，即使中继端子形成在偏离位置，中继端子的一端也可以沿贯通孔的壁被引导，使得继电器端子能够被调整到适当的位置。

4. 发明申请

US20060139857A1 Power module and its manufacturing method 有权
公开(公告)号：US20060139857A1
公开(公告)日：2006-06-29
申请号：US11105562
申请日：2005-04-14
申请人： Natsuki Tsuji
发明人： Natsuki Tsuji
IPC分类号： H01L21/50 , H02B1/00
CPC分类号： H05K3/306 , H05K1/119 , H05K1/182 , H05K3/3405 , H05K3/403 , H05K2201/09163 , H05K2201/09181 , H05K2201/09827 , H05K2201/10053 , H05K2201/10446 , H05K2201/10568 , H05K2201/10863 , H05K2203/0195 , H05K2203/167
摘要： A method of manufacturing a power module is implemented which allows easy electrical connections between a control board and relay terminals. The diameter of through holes in the control board tapers down from a side of penetration of the relay terminals in a direction of the penetration, and respective one ends of the relay terminals have a smaller diameter than the other portions of the relay terminals. The diameter of the through holes on the side of penetration of the relay terminals is made sufficiently greater than the diameter of the one ends of the relay terminals, so that the relay terminals can easily penetrate the through holes. Further, even if the relay terminals are formed in deviated positions, the one ends of the relay terminals can be guided along the walls of the through holes in the penetration, so that the relay terminals can be adjusted to proper positions.

5. 发明授权

US07777533B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07777533B2
公开(公告)日：2010-08-17
申请号：US12116570
申请日：2008-05-07
申请人： Noboru Miyamoto , Natsuki Tsuji
发明人： Noboru Miyamoto , Natsuki Tsuji
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H02M1/38 , H02M2001/385 , H03K17/0828 , H03K17/165
摘要： The present invention provides a semiconductor device includes arms formed by two semiconductor elements, a map memory device which stores therein a correlation map between a control value for each of the arms and an optimized dead time to be set for the control value or is capable of storing the same therein, drive control value acquiring means for acquiring a drive control value of each of the arms, and a dead time generating circuit for extracting the optimized dead time corresponding to the drive control value from the correlation map. The time taken until the other of the semiconductor elements is turned on after one thereof has received a command to turn off the same is the optimized dead time extracted by the dead time generating circuit.
摘要翻译：本发明提供了一种半导体器件，包括由两个半导体元件形成的臂，地图存储器件，其中存储有用于每个臂的控制值与要设置的控制值的优化死区时间之间的相关图，或者能够存储其中的驱动控制值获取装置，用于获取每个臂的驱动控制值;以及死区时间生成电路，用于从相关图提取与驱动控制值相对应的优化死区时间。在其中一个半导体元件中的一个已经接收到关闭它的命令之后，其余的半导体元件所经过的时间是由死区时间产生电路提取的优化的死区时间。

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