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1. 发明申请

US20070195949A1 Encryption processing method and encryption processing device 有权
标题翻译：加密处理方法和加密处理装置
公开(公告)号：US20070195949A1
公开(公告)日：2007-08-23
申请号：US11653879
申请日：2007-01-17
申请人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
发明人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
IPC分类号： H04L9/28
CPC分类号： H04L9/003 , G06F21/72 , G06F21/75 , G06F21/755 , H04L2209/122
摘要： An increase in safety from attacks by use of hardware-like methods by small-sized hardware is achieved. An encryption processing device includes a logical circuit capable of programmably setting logics for executing cipher processing, a memory that stores plural pieces of logical configuration information corresponding to an identical cipher processing algorithm, and a CPU that selectively sets plural logics corresponding to an identical cipher processing algorithm in the logical circuit. Even in processing using an identical cipher key, by changing the logic of the logical circuit for each processing, power consumption in cipher processing can be varied, and places a timing in which malfunctions occur can be varied. Moreover, an increase in the scale of hardware for realizing plural logics can be curbed.
摘要翻译：实现了通过使用小型硬件的类似硬件的方法的攻击来提高安全性。加密处理装置包括能够可编程地设置用于执行密码处理的逻辑的逻辑电路，存储与相同密码处理算法相对应的多条逻辑配置信息的存储器，以及选择性地设置与相同的密码处理对应的多个逻辑的CPU 算法在逻辑电路中。即使在使用相同的加密密钥的处理中，通过改变每个处理的逻辑电路的逻辑，可以改变密码处理中的功耗，并且可以改变发生故障的定时。此外，可以抑制用于实现多个逻辑的硬件规模的增加。

2. 发明授权

US08009827B2 Encryption processing method and encryption processing device 有权
标题翻译：加密处理方法和加密处理装置
公开(公告)号：US08009827B2
公开(公告)日：2011-08-30
申请号：US11653879
申请日：2007-01-17
申请人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
发明人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
IPC分类号： H04L9/28
CPC分类号： H04L9/003 , G06F21/72 , G06F21/75 , G06F21/755 , H04L2209/122
摘要： An increase in safety from attacks by use of hardware-like methods by small-sized hardware is achieved. An encryption processing device includes a logical circuit capable of programmably setting logics for executing cipher processing, a memory that stores plural pieces of logical configuration information corresponding to an identical cipher processing algorithm, and a CPU that selectively sets plural logics corresponding to an identical cipher processing algorithm in the logical circuit. Even in processing using an identical cipher key, by changing the logic of the logical circuit for each processing, power consumption in cipher processing can be varied, and places a timing in which malfunctions occur can be varied. Moreover, an increase in the scale of hardware for realizing plural logics can be curbed.
摘要翻译：实现了通过使用小型硬件的类似硬件的方法的攻击来提高安全性。加密处理装置包括能够可编程地设置用于执行密码处理的逻辑的逻辑电路，存储与相同密码处理算法相对应的多条逻辑配置信息的存储器，以及选择性地设置与相同的密码处理对应的多个逻辑的CPU 算法在逻辑电路中。即使在使用相同的加密密钥的处理中，通过改变每个处理的逻辑电路的逻辑，可以改变密码处理中的功耗，并且可以改变发生故障的定时。此外，可以抑制用于实现多个逻辑的硬件规模的增加。

3. 发明授权

US07664939B2 Method and apparatus for detecting false operation of computer 有权
标题翻译：检测计算机虚假操作的方法和装置
公开(公告)号：US07664939B2
公开(公告)日：2010-02-16
申请号：US11734361
申请日：2007-04-12
申请人： Takashi Endo , Toshio Okochi , Takashi Watanabe , Shunsuke Ota , Tatsuya Kameyama
发明人： Takashi Endo , Toshio Okochi , Takashi Watanabe , Shunsuke Ota , Tatsuya Kameyama
IPC分类号： G06F11/30 , G06F12/14 , G06F7/38 , G06F9/00
CPC分类号： G06F11/28 , G06F21/52
摘要： A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is started, the code block ID corresponding to the execution start address is written in a memory, and in the case when the control transits from the code block to other code block, by use of code block operation values obtained beforehand from these two code block IDs thereof, the code block ID in the memory is updated, and it is judged whether the updated code block ID in the memory and the code block ID allotted to the code block as the execution objective are identical or not so that a control flow error is detected.
摘要翻译：要由计算机执行的程序被分成多个代码块，并且将唯一的代码块ID分配给每个代码块。在开始执行程序的时刻，与执行开始地址相对应的代码块ID被写入存储器中，并且在控制从代码块转移到其他代码块的情况下，通过使用代码块从这两个代码块ID预先获得的操作值，存储器中的代码块ID被更新，并且判断存储器中更新的代码块ID和作为执行目标分配给代码块的代码块ID是否是相同或不相同，从而检测到控制流量错误。

4. 发明申请

US20070255980A1 METHOD AND APPARATUS FOR DETECTING FALSE OPERATION OF COMPUTER 有权
标题翻译：用于检测计算机虚拟操作的方法和装置
公开(公告)号：US20070255980A1
公开(公告)日：2007-11-01
申请号：US11734361
申请日：2007-04-12
申请人： Takashi ENDO , Toshio Okochi , Takashi Watanabe , Shunsuke Ota , Tatsuya Kameyama
发明人： Takashi ENDO , Toshio Okochi , Takashi Watanabe , Shunsuke Ota , Tatsuya Kameyama
IPC分类号： G06F11/00
CPC分类号： G06F11/28 , G06F21/52
摘要： A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is started, the code block ID corresponding to the execution start address is written in a memory, and in the case when the control transits from the code block to other code block, by use of code block operation values obtained beforehand from these two code block IDs thereof, the code block ID in the memory is updated, and it is judged whether the updated code block ID in the memory and the code block ID allotted to the code block as the execution objective are identical or not so that a control flow error is detected.
摘要翻译：要由计算机执行的程序被分成多个代码块，并且将唯一的代码块ID分配给每个代码块。在开始执行程序的时刻，与执行开始地址相对应的代码块ID被写入存储器中，并且在控制从代码块转移到其他代码块的情况下，通过使用代码块从这两个代码块ID预先获得的操作值被更新，存储器中的代码块ID被更新，并且判断存储器中更新的代码块ID和作为执行目标分配给代码块的代码块ID是否是相同或不相同，从而检测到控制流量错误。

5. 发明申请

US20090254740A1 INFORMATION PROCESSING DEVICE, ENCRYPTION METHOD OF INSTRUCTION CODE, AND DECRYPTION METHOD OF ENCRYPTED INSTRUCTION CODE 失效
标题翻译：信息处理装置，指令编码加密方法和加密指令码的分解方法
公开(公告)号：US20090254740A1
公开(公告)日：2009-10-08
申请号：US12417856
申请日：2009-04-03
申请人： Takashi Endo , Toshio Okochi , Shunsuke Ota , Tatsuya Kameyama
发明人： Takashi Endo , Toshio Okochi , Shunsuke Ota , Tatsuya Kameyama
IPC分类号： H04L9/00 , G06F21/00 , G06F9/30
CPC分类号： G06F21/72 , G06F9/3017 , G06F9/30174 , G06F9/3867 , G06F21/71 , H04L9/0631 , H04L9/088 , H04L2209/125
摘要： It is possible to achieve the protection of software with reduced overhead. For example, a memory for storing an encrypted code prepared in advance and a decryptor module for decrypting the code are provided. The decryptor module includes, for example, a three-stage pipeline and a selector for selecting one output from the outputs of each stage of the pipeline. When a branch instruction is issued and subsequent inputs of the pipeline are in the order of CD′1, CD′2, . . . , the decryptor module outputs a first decrypted code by performing a one-stage pipeline process to CD′1. Next, the decryptor module outputs a second decrypted code by performing a two-stage pipeline process to CD′2, and the decryptor module outputs a third decrypted code by performing a three-stage pipeline process to CD′3 (and subsequent codes). Therefore, in particular, the overhead to CD′1 can be reduced.
摘要翻译：可以减少开销来实现对软件的保护。例如，提供用于存储预先准备的加密代码的存储器和用于解密代码的解密器模块。解密器模块包括例如三级流水线和用于从流水线的每个级的输出中选择一个输出的选择器。当发出分支指令并且管道的后续输入是CD'1，CD'2的顺序时。。。解码器模块通过对CD'1执行一级流水线处理来输出第一解密码。接下来，解码器模块通过对CD'2执行两级流水线处理来输出第二解密码，并且解密器模块通过对CD'3（和后续码）执行三级流水线处理来输出第三解密码。因此，特别地，CD'1的开销可以降低。

6. 发明授权

US08266450B2 Information processing device, encryption method of instruction code, and decryption method of encrypted instruction code 失效
标题翻译：信息处理装置，指令码的加密方法以及加密指令码的解密方法
公开(公告)号：US08266450B2
公开(公告)日：2012-09-11
申请号：US12417856
申请日：2009-04-03
申请人： Takashi Endo , Toshio Okochi , Shunsuke Ota , Tatsuya Kameyama
发明人： Takashi Endo , Toshio Okochi , Shunsuke Ota , Tatsuya Kameyama
IPC分类号： G06F11/30
CPC分类号： G06F21/72 , G06F9/3017 , G06F9/30174 , G06F9/3867 , G06F21/71 , H04L9/0631 , H04L9/088 , H04L2209/125
摘要： It is possible to achieve the protection of software with reduced overhead. For example, a memory for storing an encrypted code prepared in advance and a decryptor module for decrypting the code are provided. The decryptor module includes, for example, a three-stage pipeline and a selector for selecting one output from the outputs of each stage of the pipeline. When a branch instruction is issued and subsequent inputs of the pipeline are in the order of CD′1, CD′2, . . . , the decryptor module outputs a first decrypted code by performing a one-stage pipeline process to CD′1. Next, the decryptor module outputs a second decrypted code by performing a two-stage pipeline process to CD′2, and the decryptor module outputs a third decrypted code by performing a three-stage pipeline process to CD′3 (and subsequent codes). Therefore, in particular, the overhead to CD′1 can be reduced.
摘要翻译：可以减少开销来实现对软件的保护。例如，提供用于存储预先准备的加密代码的存储器和用于解密代码的解密器模块。解密器模块包括例如三级流水线和用于从流水线的每个级的输出中选择一个输出的选择器。当发出分支指令并且管道的后续输入是CD'1，CD'2的顺序时。。。解码器模块通过对CD'1执行一级流水线处理来输出第一解密码。接下来，解码器模块通过对CD'2执行两级流水线处理来输出第二解密码，并且解密器模块通过对CD'3（和后续码）执行三级流水线处理来输出第三解密码。因此，特别地，CD'1的开销可以降低。

7. 发明授权

US06609366B2 Branch pipes for an exhaust manifold and method of manufacturing the same 失效
标题翻译：排气歧管用分支管及其制造方法
公开(公告)号：US06609366B2
公开(公告)日：2003-08-26
申请号：US10084450
申请日：2002-02-28
申请人： Tatsuya Kameyama
发明人： Tatsuya Kameyama
IPC分类号： F01N710
CPC分类号： F01N13/08 , F01N3/28 , F01N13/10 , F01N2260/06 , Y10T29/49398
摘要： Downstream fitting parts of exhaust manifold branch pipes which fit into a manifold container each has a sector or fan-like cross section which is formed so that the cross-section area of the downstream end of each of the branch pipes is substantially equal to that of the corresponding upstream end. During manufacture, the downstream ends of each pipe member are expanded by a predetermined amount and then shaped to have the fan or sector-like shaped cross section. This maintains the cross-sectional area of the shaped portions substantially equal to the original cross-sectional areas and therefore the cross-sectional area of the upstream ends.
摘要翻译：排气歧管分支管的下游配合部分，其装配在歧管容器中，每个分支管具有扇形或扇形横截面，其形成为使得每个分支管的下游端的横截面面积基本上等于相应的上游端。在制造过程中，每个管件的下游端部膨胀预定量，然后成形为具有扇形或扇形的横截面。这维持了成形部分的横截面面积基本上等于原始横截面积，因此保持了上游端的横截面面积。

8. 发明授权

US06259690B1 Programmable network 失效
公开(公告)号：US06259690B1
公开(公告)日：2001-07-10
申请号：US09626391
申请日：2000-07-26
申请人： Satoshi Yoshizawa , Toshiaki Suzuki , Mitsuru Ikezawa , Itaru Mimura , Tatsuya Kameyama
发明人： Satoshi Yoshizawa , Toshiaki Suzuki , Mitsuru Ikezawa , Itaru Mimura , Tatsuya Kameyama
IPC分类号： H04L1228
CPC分类号： H04L47/10 , H04L47/2441 , H04L2012/562 , H04L2012/5652 , H04L2012/5662 , H04Q11/0478
摘要： At each network node, a packet classification unit makes a judgement to transfer only a packet necessary to be processed by software to a packet processing program processor and transfer other packets directly to a routing processor. Processing history information indicating the process history executed at each network node on a network route is transferred to the other network nodes so that other network nodes can store the processing history information in respective processing history repository table. Each node refers to this table and further transfers only the packet necessary to be processed by software to the packet processing processor.

9. 发明授权

US4841521A Method and system for bidirectionally transmitting data 失效
标题翻译：双向传输数据的方法和系统
公开(公告)号：US4841521A
公开(公告)日：1989-06-20
申请号：US55036
申请日：1987-05-28
申请人： Eiichi Amada , Hirotoshi Shirasu , Hiroshi Takatori , Tohru Kazawa , Toshiro Suzuki , Takanori Miyamoto , Tatsuya Kameyama
发明人： Eiichi Amada , Hirotoshi Shirasu , Hiroshi Takatori , Tohru Kazawa , Toshiro Suzuki , Takanori Miyamoto , Tatsuya Kameyama
IPC分类号： H04L5/14
CPC分类号： H04L5/1484
摘要： A method and a system for bidirectional transmission/reception of data between two terminal stations, in which each transmission period is divided into a plurality of first time sections for relatively low speed data transmission and at least one second time section for relatively high speed data transmission, the direction of transmission between the terminal stations being predetermined in each of the first time sections, while the direction of transmission between the terminal stations is reversible in each of the second time sections, each second time section being preceded by one of the first time sections. Transmission of information data and control data is performed from one to the other terminal station in a predetermined direction in each first time section, and the direction of data transmission between the terminal stations in the next second time section is determined on the basis of control data contained in the relatively low speed data transmission.
摘要翻译：一种用于在两个终端站之间双向传输/接收数据的方法和系统，其中每个传输周期被分成用于相对低速数据传输的多个第一时间段和用于相对高速数据传输的至少一个第二时间段所述终端站之间的传输方向在所述第一时间段中的每一个中是预定的，而在所述第二时间段中的每一个中，所述终端站之间的传输方向是可逆的，每个第二时间段之前是所述第一时间段之一部分。在每个第一时间段中，以预定方向从一个终端站到另一个终端站发送信息数据和控制数据，并且基于控制数据确定下一个第二时间段中的终端站之间的数据传输方向包含在相对低速的数据传输中。

10. 发明授权

US5018134A Method for cancelling echo in a transmitter and an apparatus therefor 失效
标题翻译：用于消除发射器中的回波的方法及其装置
公开(公告)号：US5018134A
公开(公告)日：1991-05-21
申请号：US444851
申请日：1989-12-04
申请人： Masaru Kokubo , Tatsuko Shinotsuka , Tatsuya Kameyama , Motohiro Kokumai , Hirotaka Hara
发明人： Masaru Kokubo , Tatsuko Shinotsuka , Tatsuya Kameyama , Motohiro Kokumai , Hirotaka Hara
IPC分类号： H04B3/23 , H04L7/02
CPC分类号： H04B3/238 , H04B3/232 , H04B3/231
摘要： A method for cancelling an echo in a network termination (NT) of a transmission system and an apparatus therefor are disclosed. The method comprises the steps of detecting an end of transmission of a specific data train in an up-going signal when the phase of the received clock is to be shifted for synchronization during the transmission of the up-going signal from the NT, shifting the phase of the receiving clock when the end of transmission is detected, sampling a residual echo signal of the echo of the specific data train not cancelled by the adaptive filter, determining a correction value for the output of the adaptive filter and storing the correction value and adding a sign corresponding to the direction of the phase shift to the correction value after the phase shift and adding the result to the output of the adaptive filter to cancel the echo of the specific data train.

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