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1. 发明申请

US20080103708A1 Leakage power estimation 审中-公开
标题翻译：泄漏功率估计
公开(公告)号：US20080103708A1
公开(公告)日：2008-05-01
申请号：US11549165
申请日：2006-10-13
申请人： Takeshi Inoue , James D. Warnock , Douglas H. Bradley , Noah Zamdmer , Dennis Cox , Edward Nowak
发明人： Takeshi Inoue , James D. Warnock , Douglas H. Bradley , Noah Zamdmer , Dennis Cox , Edward Nowak
IPC分类号： G06F19/00 , G06F17/40
CPC分类号： G06F17/5036 , G01R31/3008 , G01R31/31721
摘要： Methods and apparatus provide for estimating leakage power as a function of delay times. Delay times and leakage power values may be measured for a test circuit of a given circuit design. A statistical sampling of the measurements may be obtained for the test circuit. The delay data and leakage power data may be correlated to express and estimate leakage power as a function of delay distribution. The test circuit may include a proposed circuit that is simulated, and the method and apparatus also may provide for: creating a schematic design of the test circuit, having, for example, defined poly gate lengths, on-chip devices, and power sources; incorporating a delay chain into the schematic design to get delay distribution data; and utilizing the schematic design, wherein the utilitzation may be a simulation.
摘要翻译：方法和装置提供了估计泄漏功率作为延迟时间的函数。对于给定电路设计的测试电路，可以测量延迟时间和漏电功率值。测试电路可以获得测量的统计采样。可以将延迟数据和泄漏功率数据相关联以表示和估计作为延迟分布的函数的泄漏功率。测试电路可以包括被仿真的所提出的电路，并且该方法和装置还可以提供：创建测试电路的示意性设计，具有例如限定的多栅极长度，片上器件和电源; 将延迟链结合到原理图设计中以获得延迟分布数据; 并且利用示意图设计，其中该功能可以是模拟。

2. 发明申请

US20070263472A1 PROCESS ENVIRONMENT VARIATION EVALUATION 审中-公开
标题翻译：过程环境变化评估
公开(公告)号：US20070263472A1
公开(公告)日：2007-11-15
申请号：US11382722
申请日：2006-05-11
申请人： Brent Anderson , Edward Nowak , Noah Zamdmer
发明人： Brent Anderson , Edward Nowak , Noah Zamdmer
IPC分类号： G11C8/00 , H01L21/8234 , H01L29/788 , H01L21/336
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.
摘要翻译：公开了用于评估过程环境变化的影响的结构和方法。公开了一种结构和相关方法，其包括以非共线方式布置的多个电结构，用于确定多个电结构附近的工艺环境变化的大小和方向。多个结构可以包括耦合到第二极性FET的第一极性FET，第一极性FET和第二极性FET中的每一个耦合到第一焊盘和第二焊盘，使得该结构允许独立测量第一极性FET 和仅使用第一和第二焊盘的第二极性FET。或者，电气结构可以包括电阻器，二极管或环形振荡器。每个电气结构的适当测量允许确定包括过程环境变化的影响的幅度和方向的梯度场。

3. 发明申请

US20130088248A1 DETERMINATION OF SERIES RESISTANCE OF AN ARRAY OF CAPACITIVE ELEMENTS 有权
标题翻译：确定电容元件阵列的电阻率
公开(公告)号：US20130088248A1
公开(公告)日：2013-04-11
申请号：US13269830
申请日：2011-10-10
申请人： Noah Zamdmer
发明人： Noah Zamdmer
IPC分类号： G01R27/02
CPC分类号： G11C29/50016 , G11C11/40 , G11C2029/5002 , H03K3/0315 , H03L7/0995
摘要： A circuit for determination of a resistance of an array of capacitive elements includes a reference ring oscillator circuit, the reference ring oscillator circuit being loaded with low-loss capacitive elements; an array test ring oscillator circuit, the array test ring oscillator circuit being loaded with the array of capacitive elements; and a resistance determination module, the resistance determination module configured to determine the resistance of the array of capacitive elements based on data from the reference ring oscillator circuit and the array test ring oscillator circuit.
摘要翻译：用于确定电容元件阵列的电阻的电路包括参考环形振荡器电路，参考环形振荡器电路装载有低损耗电容元件; 阵列测试环振荡器电路，阵列测试环振荡器电路装载有电容元件阵列; 电阻确定模块，其被配置为基于来自参考环形振荡器电路和阵列测试环振荡器电路的数据来确定电容元件阵列的电阻。

4. 发明授权

US09047990B2 Determination of series resistance of an array of capacitive elements 有权
标题翻译：确定电容元件阵列的串联电阻
公开(公告)号：US09047990B2
公开(公告)日：2015-06-02
申请号：US13269830
申请日：2011-10-10
申请人： Noah Zamdmer
发明人： Noah Zamdmer
IPC分类号： H03K3/03 , G01R27/08 , G11C29/50 , H03L7/099 , G11C11/40
CPC分类号： G11C29/50016 , G11C11/40 , G11C2029/5002 , H03K3/0315 , H03L7/0995
摘要： A circuit for determination of a resistance of an array of capacitive elements includes a reference ring oscillator circuit, the reference ring oscillator circuit being loaded with low-loss capacitive elements; an array test ring oscillator circuit, the array test ring oscillator circuit being loaded with the array of capacitive elements; and a resistance determination module, the resistance determination module configured to determine the resistance of the array of capacitive elements based on data from the reference ring oscillator circuit and the array test ring oscillator circuit.
摘要翻译：用于确定电容元件阵列的电阻的电路包括参考环形振荡器电路，参考环形振荡器电路装载有低损耗电容元件; 阵列测试环振荡器电路，阵列测试环振荡器电路装载有电容元件阵列; 电阻确定模块，其被配置为基于来自参考环形振荡器电路和阵列测试环振荡器电路的数据来确定电容元件阵列的电阻。

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