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1. 发明申请

US20090013022A1 Multiplier Engine Apparatus and Method 失效
标题翻译：乘法器发动机装置及方法
公开(公告)号：US20090013022A1
公开(公告)日：2009-01-08
申请号：US11773558
申请日：2007-07-05
申请人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
发明人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
IPC分类号： G06F7/523
CPC分类号： G06F7/5338 , G06F7/5318
摘要： A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit 0 position.
摘要翻译：提供了减少用于提供乘法器引擎的电路的大小以及增加执行乘法算法的速度的乘法器引擎。示例性实施例可以包括具有一个或多个仅包括两个全加器的4：2压缩机的M * 8乘法引擎，与已知的5：2基于压缩机的架构中的三个全加器相反。 4：2压缩机能够通过使用部分乘积输入的最不重要部分中的未使用位来存储否定位值来实现与已知的5：2基于压缩器的架构相同的操作。此外，与部分积输入不融合的否定位值可以输入到位0位置的4：2压缩器。

2. 发明授权

US06742014B2 Conditional carry encoding for carry select adder 失效
标题翻译：进位选择加法器的条件进位编码
公开(公告)号：US06742014B2
公开(公告)日：2004-05-25
申请号：US10259015
申请日：2002-09-27
申请人： Douglas H. Bradley
发明人： Douglas H. Bradley
IPC分类号： G06F750
CPC分类号： G06F7/507
摘要： The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.
摘要翻译：本发明的机构以两位流的二进制加法对每个地方的进位和操作数位进行编码。相对于一个位块的进位，进位被编码为传播（Pin），Kill（Kin）和Generate（Gin）。任何时候只有一个信号会很高，另外两个信号会很低。位的Pin信号是真实的，其中该位具有与进位到位的进位相同的进位，即，到该块的进位传播到特定位。一个位的Kin信号是正确的，其中进位到该位是零，而不管进位到块，即，到达该块的任何进位在它到达位之前被杀死。一位的Gin信号是真的，其中该位具有一个进位，而不管进位到该块，即在该块内产生该位的进位。这些信号用于计算操作数位的和。

3. 发明授权

US06496846B1 Conditional carry encoding for carry select adder 失效
标题翻译：进位选择加法器的条件进位编码
公开(公告)号：US06496846B1
公开(公告)日：2002-12-17
申请号：US09352259
申请日：1999-07-13
申请人： Douglas H. Bradley
发明人： Douglas H. Bradley
IPC分类号： G06F750
CPC分类号： G06F7/507
摘要： The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.
摘要翻译：本发明的机构以两位流的二进制加法对每个地方的进位和操作数位进行编码。相对于一个位块的进位，进位被编码为传播（Pin），Kill（Kin）和Generate（Gin）。任何时候只有一个信号会很高，另外两个信号会很低。位的Pin信号是真实的，其中该位具有与进位到位的进位相同的进位，即，到该块的进位传播到特定位。一个位的Kin信号是正确的，其中进位到该位是零，而不管进位到块，即，到达该块的任何进位在它到达位之前被杀死。一位的Gin信号是真的，其中该位具有一个进位，而不管进位到该块，即在该块内产生该位的进位。这些信号用于计算操作数位的和。

4. 发明授权

US07958180B2 Multiplier engine 失效
标题翻译：乘法引擎
公开(公告)号：US07958180B2
公开(公告)日：2011-06-07
申请号：US11773558
申请日：2007-07-05
申请人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
发明人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/5318
摘要： A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit 0 position.
摘要翻译：提供了减少用于提供乘法器引擎的电路的大小以及增加执行乘法算法的速度的乘法器引擎。示例性实施例可以包括具有一个或多个仅包括两个全加器的4：2压缩机的M * 8乘法引擎，与已知的5：2基于压缩机的架构中的三个全加器相反。 4：2压缩机能够通过使用部分乘积输入的最不重要部分中的未使用位来存储否定位值来实现与已知的5：2基于压缩器的架构相同的操作。此外，与部分积输入不融合的否定位值可以输入到位0位置的4：2压缩器。

5. 发明授权

US07447602B1 System and method for sorting processors based on thermal design point 失效
标题翻译：基于热设计点对处理器进行分类的系统和方法
公开(公告)号：US07447602B1
公开(公告)日：2008-11-04
申请号：US11758034
申请日：2007-06-05
申请人： Douglas H. Bradley , Jonathan J. DeMent , Sang H. Dhong , Brian Flachs , Gilles Gervais , Yoichi Nishino
发明人： Douglas H. Bradley , Jonathan J. DeMent , Sang H. Dhong , Brian Flachs , Gilles Gervais , Yoichi Nishino
IPC分类号： G01R21/00 , G01R21/06
CPC分类号： G01R31/31721 , G01R31/31718
摘要： A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.
摘要翻译：提供了一种基于热设计点分类处理器芯片的系统和方法。利用系统和方法，对于每个处理器芯片，在处理器芯片上运行高功率工作负载以确定电压调节器模块（VRM）负载线。此后，将热设计点（TDP）工作量应用于处理器芯片，并且改变电压直到处理器芯片的性能落在VRM负载线上。此时，对处理器芯片的电源输入进行测量并用于对处理器芯片进行排序或分页。应用的各种工作负载具有恒定的频率。从处理器芯片的这种排序中，可以识别需要较少电压以实现期望频率的低速处理器和在期望频率下运行时消耗较少电流的低电流处理器。

6. 发明申请

US20080103708A1 Leakage power estimation 审中-公开
标题翻译：泄漏功率估计
公开(公告)号：US20080103708A1
公开(公告)日：2008-05-01
申请号：US11549165
申请日：2006-10-13
申请人： Takeshi Inoue , James D. Warnock , Douglas H. Bradley , Noah Zamdmer , Dennis Cox , Edward Nowak
发明人： Takeshi Inoue , James D. Warnock , Douglas H. Bradley , Noah Zamdmer , Dennis Cox , Edward Nowak
IPC分类号： G06F19/00 , G06F17/40
CPC分类号： G06F17/5036 , G01R31/3008 , G01R31/31721
摘要： Methods and apparatus provide for estimating leakage power as a function of delay times. Delay times and leakage power values may be measured for a test circuit of a given circuit design. A statistical sampling of the measurements may be obtained for the test circuit. The delay data and leakage power data may be correlated to express and estimate leakage power as a function of delay distribution. The test circuit may include a proposed circuit that is simulated, and the method and apparatus also may provide for: creating a schematic design of the test circuit, having, for example, defined poly gate lengths, on-chip devices, and power sources; incorporating a delay chain into the schematic design to get delay distribution data; and utilizing the schematic design, wherein the utilitzation may be a simulation.
摘要翻译：方法和装置提供了估计泄漏功率作为延迟时间的函数。对于给定电路设计的测试电路，可以测量延迟时间和漏电功率值。测试电路可以获得测量的统计采样。可以将延迟数据和泄漏功率数据相关联以表示和估计作为延迟分布的函数的泄漏功率。测试电路可以包括被仿真的所提出的电路，并且该方法和装置还可以提供：创建测试电路的示意性设计，具有例如限定的多栅极长度，片上器件和电源; 将延迟链结合到原理图设计中以获得延迟分布数据; 并且利用示意图设计，其中该功能可以是模拟。

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