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1. 发明授权

US07684270B2 Equalizer circuit and method of controlling the same 有权
标题翻译：均衡电路及其控制方法
公开(公告)号：US07684270B2
公开(公告)日：2010-03-23
申请号：US11892488
申请日：2007-08-23
申请人： Takuya Hirota , Takao Yanagida , Hiroyuki Takahashi
发明人： Takuya Hirota , Takao Yanagida , Hiroyuki Takahashi
IPC分类号： G11C7/02
CPC分类号： G11C11/4094 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C2207/2281
摘要： In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD−Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.
摘要翻译：在传统的均衡器电路中，在将具有预定电压差的布线对的电压设定为相同的均衡操作中，使配线的电压成对地收敛到具有偏移的电压需要很长时间相对于均衡动作后的配线对的电压的中点电压。根据本发明的均衡器电路，提供了将第一布线（SAP）和第二布线（SAN）的电压设置为基本相同的并具有第一晶体管（N1）的均衡器电路（50）连接在第一布线（SAP）和连接在第一布线SAP和第二布线（SAN）之间的第一电源电路（例如，HVDD-Va）和第二晶体管（N2）之间。均衡器电路50使第一晶体管（N1）导通，然后使第二晶体管（N2）导通。

2. 发明授权

US07489576B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07489576B2
公开(公告)日：2009-02-10
申请号：US11723830
申请日：2007-03-22
申请人： Takuya Hirota , Takao Yanagida
发明人： Takuya Hirota , Takao Yanagida
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/08 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.
摘要翻译：一种半导体存储装置具有包括存储数据的多个存储单元的第一和第二单元阵列，选择性地与第一和第二单元阵列中的任一个连接的读出放大器，第一预充电电路，用于在第一和第二单元阵列中设置一对位线单元阵列到预定电压，第二预充电电路，用于将第二单元阵列中的一对位线设置为预定电压;第一开关电路，用于将读出放大器与第一单元阵列连接;第二开关电路，具有第二单元阵列的读出放大器和用于控制第一和第二开关电路的导通状态的开关控制器。在非选择状态，其中读出放大器不访问任何单元阵列，开关控制器将开关电路之一控制为导通状态。

3. 发明授权

US08045409B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08045409B2
公开(公告)日：2011-10-25
申请号：US12603879
申请日：2009-10-22
申请人： Takuya Hirota , Takao Yanagida
发明人： Takuya Hirota , Takao Yanagida
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/41 , G11C29/12 , G11C29/50 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.
摘要翻译：半导体存储器件包括布置在字线与位线对的交点处的多个存储器单元，为每个位线对布置的预充电电路，并且被配置为对每个位线对进行预充电;以及一个Y开关电路，其被布置用于每个位线对并被配置为选择每个位线对。半导体存储装置还包括模式切换单元，其根据外部提供的模式选择信号切换正常模式和测试模式，多个单独控制单元，其根据操作控制每个预充电电路的操作的正常模式中的Y开关电路，以及在测试模式下共同地关闭所有预充电电路的块控制单元。

4. 发明授权

US07692988B2 Semiconductor device and method of controlling the same 失效
标题翻译：半导体装置及其控制方法
公开(公告)号：US07692988B2
公开(公告)日：2010-04-06
申请号：US12168986
申请日：2008-07-08
申请人： Takao Yanagida , Takuya Hirota
发明人： Takao Yanagida , Takuya Hirota
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1009 , G11C11/4096
摘要： A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.
摘要翻译：根据本发明的一个实施例的半导体器件（DRAM）包括连接到存储器单元的多对数字线（数字True，Not），连接到存储单元的公共信号线对（主I / O True，否）多个数字线对，主I / O均衡器，执行公共信号线对的预充电，以及控制电路，确定预充电操作是否继续，而与外部输入的屏蔽信号的信号电平无关。

5. 发明申请

US20080049530A1 Equalizer circuit and method of controlling the same 有权
标题翻译：均衡电路及其控制方法
公开(公告)号：US20080049530A1
公开(公告)日：2008-02-28
申请号：US11892488
申请日：2007-08-23
申请人： Takuya Hirota , Takao Yanagida , Hiroyuki Takahashi
发明人： Takuya Hirota , Takao Yanagida , Hiroyuki Takahashi
IPC分类号： G11C11/4091 , G05F1/00
CPC分类号： G11C11/4094 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C2207/2281
摘要： In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD−Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.
摘要翻译：在传统的均衡器电路中，在将具有预定电压差的布线对的电压设定为相同的均衡操作中，使配线的电压成对地收敛到具有偏移的电压需要很长时间相对于均衡动作后的配线对的电压的中点电压。根据本发明的均衡器电路，提供了一种均衡器电路（50），其将第一布线（SAP）和第二布线（SAN）的电压设置为基本相同，并且具有第一晶体管（N 1 ）连接在第一布线（SAP）和第一电源电路（例如，HVDD-Va）之间，第二晶体管（N 2）连接在第一布线SAP和第二布线（SAN）之间。均衡电路50使第一晶体管（N1）导通，然后使第二晶体管（N 2）导通。

6. 发明申请

US20090016123A1 SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME 失效
标题翻译：半导体器件及其控制方法
公开(公告)号：US20090016123A1
公开(公告)日：2009-01-15
申请号：US12168986
申请日：2008-07-08
申请人： Takao Yanagida , Takuya Hirota
发明人： Takao Yanagida , Takuya Hirota
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1009 , G11C11/4096
摘要： A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.
摘要翻译：根据本发明的一个实施例的半导体器件（DRAM）包括连接到存储器单元的多对数字线（数字True，Not），连接到存储单元的公共信号线对（主I / O True，否）多个数字线对，主I / O均衡器，执行公共信号线对的预充电，以及控制电路，确定预充电操作是否继续，而与外部输入的屏蔽信号的信号电平无关。

7. 发明申请

US20070223297A1 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US20070223297A1
公开(公告)日：2007-09-27
申请号：US11723830
申请日：2007-03-22
申请人： Takuya Hirota , Takao Yanagida
发明人： Takuya Hirota , Takao Yanagida
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/08 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.
摘要翻译：一种半导体存储装置具有包括存储数据的多个存储单元的第一和第二单元阵列，选择性地与第一和第二单元阵列中的任一个连接的读出放大器，第一预充电电路，用于在第一和第二单元阵列中设置一对位线单元阵列到预定电压，第二预充电电路，用于将第二单元阵列中的一对位线设置为预定电压;第一开关电路，用于将读出放大器与第一单元阵列连接;第二开关电路，具有第二单元阵列的读出放大器和用于控制第一和第二开关电路的导通状态的开关控制器。在非选择状态，其中读出放大器不访问任何单元阵列，开关控制器将开关电路之一控制为导通状态。

8. 发明申请

US20050237848A1 Semiconductor memory device and semiconductor device and semiconductor memory device control method 有权
标题翻译：半导体存储器件和半导体器件及半导体存储器件控制方法
公开(公告)号：US20050237848A1
公开(公告)日：2005-10-27
申请号：US10507117
申请日：2004-09-10
申请人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
IPC分类号： H01L21/822 , G11C11/407 , G11C11/4074 , G11C11/4076 , H01L27/04 , H03K5/14 , G11C8/02
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译：电池芯单元及其外围电路由相对低压的电源驱动。提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。读出放大器将位线的较高电压电平放大到电源电压。然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟，降低所提供的电源电压。

9. 发明授权

US06331959B1 Semiconductor memory device and control method thereof 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US06331959B1
公开(公告)日：2001-12-18
申请号：US09525611
申请日：2000-03-14
申请人： Takuya Hirota
发明人： Takuya Hirota
IPC分类号： G11C700
CPC分类号： G11C11/419 , G11C7/06
摘要： A semiconductor storage device is disclosed that can lower sense amplifier input potentials to about a half supply potential (VCC/2) to speed up sense amplifier operations. According to one embodiment, a semiconductor storage device (100) may include a pair of digit lines (104 and 106), a memory cell (108) that can place stored data on digit lines (104 and 106), a sense amplifier (112) that may read memory cell data on digit lines (104 and 106), and switching devices (120-a and 120-b) connected between sense amplifier inputs (112-a and 112-b) and digit lines (104 and 106). Digit lines (104 and 106) may be precharged to a high potential. Memory cell data may then be placed on the digit lines (104 and 106). Prior to the activation of the sense amplifier (112) switching devices (120-a and 120-b) may lower the digit line potentials to a level more conducive to sensing by the sense amplifier (112). In this way, a read operation by the sense amplifier (112) may be faster than conventional approaches.
摘要翻译：公开了一种半导体存储装置，其可将感测放大器输入电位降低到大约一半的电源电位（VCC / 2），以加速感测放大器的操作。根据一个实施例，半导体存储设备（100）可以包括一对数字线（104和106），可将存储的数据放置在数字线（104和106）上的存储单元（108），读出放大器（112）），其可读取数字线（104和106）上的存储单元数据以及连接在感测放大器输入（112-a和112-b）与数字线（104和106）之间的开关装置（120-a和120-b）。数字线（104和106）可以被预充电到高电位。然后可将存储单元数据放置在数字线（104和106）上。在激活读出放大器（112）之前，开关器件（120-a和120-b）可以将数字线电位降低到更有利于读出放大器（112）感测的电平。以这种方式，读出放大器（112）的读取操作可能比传统的方法更快。

10. 发明授权

US6101122A Data latch circuit 有权
标题翻译：数据锁存电路
公开(公告)号：US6101122A
公开(公告)日：2000-08-08
申请号：US273488
申请日：1999-03-22
申请人： Takuya Hirota
发明人： Takuya Hirota
IPC分类号： G11C11/417 , G11C11/409 , G11C16/06 , H03K3/037 , G11C7/00
CPC分类号： H03K3/0375
摘要： A data latch circuit includes a differential amplifier for detecting a potential difference between a pair of signal transmission lines for transmitting a pair of complementary signals, a latch timing signal generator for generating a latch timing signal based on the detection by the differential amplifier, and a latch section for responding to the latch timing signal to latch the complementary signals transferred thereto. A reliable and high-speed signal transmission can be achieved even in a semiconductor device having a large chip size.
摘要翻译：数据锁存电路包括：差分放大器，用于检测用于发送一对互补信号的一对信号传输线之间的电位差;基于差分放大器的检测产生锁存定时信号的锁存定时信号发生器;以及锁存部分，用于响应锁存定时信号以锁存传送到其上的互补信号。即使在具有大芯片尺寸的半导体器件中也可以实现可靠且高速的信号传输。

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