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1. 发明申请

US20160173131A1 Method and Apparatus of a Fully-Pipelined Layered LDPC Decoder 审中-公开
标题翻译：全流水线分层LDPC解码器的方法和装置
公开(公告)号：US20160173131A1
公开(公告)日：2016-06-16
申请号：US15011252
申请日：2016-01-29
申请人： Tensorcom, Inc.
发明人： Bo Xia , Ricky Lap Kei Cheung , Bo Lu
IPC分类号： H03M13/11
CPC分类号： H03M13/1145 , H03M13/1122 , H03M13/114 , H03M13/1148 , H03M13/116
摘要： Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.
摘要翻译：处理器被布置在流水线结构中以在多层数据上操作，每层包括多组数据。存储器的输入耦合到流水线中的最后一个处理器的输出，并且存储器的输出耦合到流水线中的第一处理器的输入。在流水线中执行多路复用和解复用操作。对于每个层中的每个组，将从存储器读取的存储结果应用于流水线结构中的第一处理器。存储结果的计算结果在最后一个处理器处输出并存储在存储器中。一旦对第一层中的最后一组数据的处理完成，相应的处理器被配置为在管线完成对第一层的处理之前处理下一层中的数据。从下一层获得的存储结果包括从第一层之前的层产生的计算结果。

2. 发明授权

US09450537B2 Method and apparatus to detect LO leakage and image rejection using a single transistor 有权
标题翻译：使用单个晶体管检测LO泄漏和图像抑制的方法和装置
公开(公告)号：US09450537B2
公开(公告)日：2016-09-20
申请号：US14467075
申请日：2014-08-25
申请人： Tensorcom, Inc.
发明人： KhongMeng Tham , Huainan Ma , Zaw Soe , Ricky Lap Kei Cheung
IPC分类号： G06G7/12 , H03D3/00 , H03D7/16
CPC分类号： H04B1/0475 , H03C2200/0058 , H03D3/008 , H03D3/009 , H03D7/125 , H03D7/165 , H04B1/04 , H04B1/0458 , H04B2001/0408
摘要： LO leakage and Image are common and undesirable effects in typical transmitters. Typically, thirty complex hardware and algorithms are used to calibrate and reduce these two impairments. A single transistor that draws essentially no de current and occupies a very small area, is used to detect the LO leakage and Image Rejection signals. The single transistor operating as a square law device, is used to mix the signals at the input and output ports of the power amplifier (PA). The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.
摘要翻译： LO泄漏和图像在典型的发射器中是常见的和不良影响。通常，使用三十个复杂的硬件和算法来校准和减少这两个损伤。基本上没有去电流并占据非常小的面积的单个晶体管用于检测LO泄漏和图像抑制信号。作为平方律器件工作的单个晶体管用于混合功率放大器（PA）输入和输出端口的信号。由单个晶体管产生的混合信号可以同时校准LO泄漏和图像抑制。

3. 发明授权

US09391817B2 Method and apparatus of an architecture to switch equalization based on signal delay spread 有权
标题翻译：基于信号延迟扩展来切换均衡的架构的方法和装置
公开(公告)号：US09391817B2
公开(公告)日：2016-07-12
申请号：US14223516
申请日：2014-03-24
申请人： Tensorcom, Inc.
发明人： Ricky Lap Kei Cheung
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/03 , H04L27/26 , H04L25/02
CPC分类号： H04L25/03159 , H04L25/0212 , H04L25/03019 , H04L27/2647 , H04L2025/03414
摘要： The 60 GHz channel between the transmitter and receiver can have AWGN characteristics allowing a Time Domain Equalizer (TDE) to be used at the receiver instead of a Frequency Domain Equalizer (FDE). The complexity of performing matrix inversion on a received signal is reduced when directional antennas are used in a 60 GHz system. Incorporating the TDE in place of the FDE saves almost an order of magnitude in power dissipation. For portable units, such a savings is beneficial since the battery life can be extended. The signal quality of wireless channel is based on the characteristics of the received signal to switch the equalization operation from a system performing FDE to TDE and vice versa. The receiver adapts to the received signal to reduce the power dissipation of the system.
摘要翻译：发射机和接收机之间的60 GHz信道可以具有AWGN特性，允许在接收机而不是频域均衡器（FDE）使用时域均衡器（TDE）。当在60GHz系统中使用定向天线时，对接收信号执行矩阵反演的复杂度降低。结合TDE代替FDE节省了功耗的几乎一个数量级。对于便携式设备，这样的节省是有益的，因为电池寿命可以延长。无线信道的信号质量基于接收信号的特性，以将均衡操作从执行FDE的系统切换到TDE，反之亦然。接收机适应接收到的信号，以减少系统的功耗。

4. 发明申请

US20160056764A1 Method and Apparatus to Detect LO Leakage and Image Rejection using a Single Transistor 有权
标题翻译：使用单晶体管检测LO泄漏和图像抑制的方法和装置
公开(公告)号：US20160056764A1
公开(公告)日：2016-02-25
申请号：US14467075
申请日：2014-08-25
申请人： Tensorcom, Inc.
发明人： KhongMeng Tham , Huainan Ma , Zaw Soe , Ricky Lap Kei Cheung
IPC分类号： H03D7/14
CPC分类号： H04B1/0475 , H03C2200/0058 , H03D3/008 , H03D3/009 , H03D7/125 , H03D7/165 , H04B1/04 , H04B1/0458 , H04B2001/0408
摘要： LO leakage and Image are common and undesirable effects in typical transmitters. Typically, thirty complex hardware and algorithms are used to calibrate and reduce these two impairments. A single transistor that draws essentially no de current and occupies a very small area, is used to detect the LO leakage and Image Rejection signals. The single transistor operating as a square law device, is used to mix the signals at the input and output ports of the power amplifier (PA). The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.
摘要翻译： LO泄漏和图像在典型的发射器中是常见的和不良影响。通常，使用三十个复杂的硬件和算法来校准和减少这两个损伤。基本上没有去电流并占据非常小的面积的单个晶体管用于检测LO泄漏和图像抑制信号。作为平方律器件工作的单个晶体管用于混合功率放大器（PA）输入和输出端口的信号。由单个晶体管产生的混合信号可以同时校准LO泄漏和图像抑制。

5. 发明申请

US20190007076A1 METHOD AND APPARATUS TO DETECT LO LEAKAGE AND IMAGE REJECTION USING A SINGLE TRANSISTOR 审中-公开
公开(公告)号：US20190007076A1
公开(公告)日：2019-01-03
申请号：US16122669
申请日：2018-09-05
申请人： Tensorcom, Inc.
发明人： KhongMeng Tham , Huainan Ma , Zaw Soe , Ricky Lap Kei Cheung
IPC分类号： H04B1/04 , H03D7/16 , H03D3/00 , H03D7/12
摘要： Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

6. 发明授权

US09418047B2 Method and apparatus of a fully-pipelined FFT 有权
标题翻译：全流水线FFT的方法和装置
公开(公告)号：US09418047B2
公开(公告)日：2016-08-16
申请号：US14192725
申请日：2014-02-27
申请人： Tensorcom, Inc.
发明人： Bo Lu , Ricky Lap Kei Cheung , Bo Xia
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A plurality of three bit units (called triplets) are permuted by a shuffler to shuffle the positions of the triplets into different patterns which are used to specific the read/write operation of a memory. For example, the least significant triplet in a conventional counter can be placed in the most significant position of a permuted three triplet pattern. The count of this permuted counter triplet generates addresses that jump 64 positions each clock cycle. These permutations can then be used to generate read and write control information to read from/write to memory banks conducive for efficient Radix-8 Butterfly operation. In addition, one or more triplets can also determine if a barrel shifter or right circular shift is required to shift data from one data lane to a second data lane. The triplets allow efficient FFT operation in a pipelined structure.
摘要翻译：多个三位单元（称为三元组）由洗牌器置换，以将三元组的位置洗牌到用于特定存储器的读/写操作的不同模式中。例如，常规计数器中的最低有效三重态可以被置于置换的三重态图案的最重要位置。这个置换的计数器三元组的计数产生每个时钟周期跳转64个位置的地址。然后可以使用这些排列来产生读/写控制信息，从而有助于高效的“八只蝴蝶”操作从存储器库读/写。此外，一个或多个三元组还可以确定是否需要桶形移位器或右循环移位来将数据从一个数据通道移动到第二数据通道。三元组允许在流水线结构中进行有效的FFT运算。

7. 发明申请

US20150270993A1 Method and Apparatus of an Architecture to Switch Equalization Based on Signal Delay Spread 有权
标题翻译：基于信号延迟传播的开关均衡的架构方法与装置
公开(公告)号：US20150270993A1
公开(公告)日：2015-09-24
申请号：US14223516
申请日：2014-03-24
申请人： Tensorcom, Inc.
发明人： Ricky Lap Kei Cheung
IPC分类号： H04L25/03 , H04L27/26
CPC分类号： H04L25/03159 , H04L25/0212 , H04L25/03019 , H04L27/2647 , H04L2025/03414
摘要： The 60 GHz channel between the transmitter and receiver can have AWGN characteristics allowing a Time Domain Equalizer (TDE) to be used at the receiver instead of a Frequency Domain Equalizer (FDE). The complexity of performing matrix inversion on a received signal is reduced when directional antennas are used in a 60 GHz system. Incorporating the TDE in place of the FDE saves almost an order of magnitude in power dissipation. For portable units, such a savings is beneficial since the battery life can be extended. The signal quality of wireless channel is based on the characteristics of the received signal to switch the equalization operation from a system performing FDE to TDE and vice versa. The receiver adapts to the received signal to reduce the power dissipation of the system.
摘要翻译：发射机和接收机之间的60 GHz信道可以具有AWGN特性，允许在接收机而不是频域均衡器（FDE）使用时域均衡器（TDE）。当在60GHz系统中使用定向天线时，对接收信号执行矩阵反演的复杂度降低。结合TDE代替FDE节省了功耗的几乎一个数量级。对于便携式设备，这样的节省是有益的，因为电池寿命可以延长。无线信道的信号质量基于接收信号的特性，以将均衡操作从执行FDE的系统切换到TDE，反之亦然。接收机适应接收到的信号，以减少系统的功耗。

8. 发明授权

US10778250B2 Method and apparatus of a fully-pipelined layered LDPC decoder 有权
公开(公告)号：US10778250B2
公开(公告)日：2020-09-15
申请号：US16277890
申请日：2019-02-15
申请人： TensorCom, Inc.
发明人： Bo Xia , Ricky Lap Kei Cheung , Bo Lu
IPC分类号： H03M13/11
摘要： Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

9. 发明申请

US20190222227A1 METHOD AND APPARATUS OF A FULLY-PIPELINED LAYERED LDPC DECODER 审中-公开
公开(公告)号：US20190222227A1
公开(公告)日：2019-07-18
申请号：US16277890
申请日：2019-02-15
申请人： TensorCom, Inc.
发明人： Bo Xia , Ricky Lap Kei Cheung , Bo Lu
IPC分类号： H03M13/11
CPC分类号： H03M13/1145 , H03M13/1122 , H03M13/114 , H03M13/1148 , H03M13/116
摘要： Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

10. 发明授权

US10250280B2 Method and apparatus of a fully-pipelined layered LDPC decoder 有权
公开(公告)号：US10250280B2
公开(公告)日：2019-04-02
申请号：US15011252
申请日：2016-01-29
申请人： Tensorcom, Inc.
发明人： Bo Xia , Ricky Lap Kei Cheung , Bo Lu
IPC分类号： H03M13/11
摘要： Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

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