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1. 发明授权

US07939894B2 Isolated high performance FET with a controllable body resistance 有权
标题翻译：隔离式高性能FET，具有可控制的体电阻
公开(公告)号：US07939894B2
公开(公告)日：2011-05-10
申请号：US12185368
申请日：2008-08-04
申请人： Terence B. Hook , Jenny Hu , Jae-Eun Park
发明人： Terence B. Hook , Jenny Hu , Jae-Eun Park
IPC分类号： H01L21/70
CPC分类号： H01L27/0738 , H01L29/78
摘要： The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active body region of the bulk semiconductor substrate, wherein the body resistor provides for adjustability of the body potential of the semiconductor devices. In another aspect the present invention provides a semiconductor device including a bulk semiconductor substrate, at least one field effect transistor formed on the bulk semiconductor substrate including an isolated active body region, and a resistor in electrical communication with the isolated active body region.
摘要翻译：本发明提供了一种控制电气装置中的偏置的方法，包括提供在体半导体衬底上的半导体器件，每个半导体器件包括与相邻器件的有源体区隔离的有源体区域，以及提供与电极接触的体电阻器活体体区域，其中体电阻器提供半导体器件的体电位的可调节性。在另一方面，本发明提供了一种半导体器件，其包括体半导体衬底，形成在包括隔离的有源体区域的体半导体衬底上的至少一个场效应晶体管和与隔离的有源体区域电连通的电阻器。

2. 发明申请

US20080157159A1 HIGHLY TUNABLE METAL-ON-SEMICONDUCTOR VARACTOR 审中-公开
标题翻译：高可控金属 - 半导体变送器
公开(公告)号：US20080157159A1
公开(公告)日：2008-07-03
申请号：US11617322
申请日：2006-12-28
申请人： Terence B. Hook , Jae-Eun Park
发明人： Terence B. Hook , Jae-Eun Park
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/945
摘要： A metal-on-semiconductor varactor with a high value of Cmax/Cmin comprises a semiconductor bottom plate with an array of semiconductor pillars. The pillars may be in an accumulation mode to provide a high capacitance or in a depletion mode to provide a low capacitance. The maximum capacitance in an accumulation mode is primarily determined by the capacitance of the semiconductor pillars. The minimum capacitance in a depletion mode is primarily determined by a capacitor formed on an inter-pillar semiconductor surface between the semiconductor pillars. The minimum capacitance, and hence the value of Cmax/Cmin may be tuned by adjusting process parameters, design parameters and by alterations in the MOS varactor structure such as forming a highly doped semiconductor layer beneath the inter-pillar semiconductor surface or forming a plate insulator.
摘要翻译：具有高值C max / C min以上的金属半导体变容二极管包括具有半导体柱阵列的半导体底板。柱可以处于累积模式以提供高电容或耗尽模式以提供低电容。累积模式下的最大电容主要由半导体支柱的电容决定。耗尽模式中的最小电容主要由形成在半导体柱之间的柱间半导体表面上的电容器决定。可以通过调整工艺参数，设计参数和通过MOS变容二极管结构中的改变来调整最小电容，并因此调整最小电容值，并因此调整最小电容值，例如形成柱内半导体表面下方的高度掺杂的半导体层或形成板绝缘体。

3. 发明申请

US20100025769A1 ISOLATED HIGH PERFORMANCE FET WITH A CONTROLLABLE BODY RESISTANCE 有权
标题翻译：具有可控制体电阻的隔离型高性能FET
公开(公告)号：US20100025769A1
公开(公告)日：2010-02-04
申请号：US12185368
申请日：2008-08-04
申请人： Terence B. Hook , Jenny Hu , Jaee-Eun Park
发明人： Terence B. Hook , Jenny Hu , Jaee-Eun Park
IPC分类号： H01L27/06 , H01L21/8238
CPC分类号： H01L27/0738 , H01L29/78
摘要： The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active body region of the bulk semiconductor substrate, wherein the body resistor provides for adjustability of the body potential of the semiconductor devices. In another aspect the present invention provides a semiconductor device including a bulk semiconductor substrate, at least one field effect transistor formed on the bulk semiconductor substrate including an isolated active body region, and a resistor in electrical communication with the isolated active body region.
摘要翻译：本发明提供了一种控制电气装置中的偏置的方法，包括提供在体半导体衬底上的半导体器件，每个半导体器件包括与相邻器件的有源体区隔离的有源体区域，以及提供与电极接触的体电阻器活体体区域，其中体电阻器提供半导体器件的体电位的可调节性。在另一方面，本发明提供了一种半导体器件，其包括体半导体衬底，形成在包括隔离的有源体区域的体半导体衬底上的至少一个场效应晶体管和与隔离的有源体区域电连通的电阻器。

4. 发明授权

US08619979B2 Physically unclonable function implemented through threshold voltage comparison 失效
标题翻译：通过阈值电压比较实现物理不可克隆功能
公开(公告)号：US08619979B2
公开(公告)日：2013-12-31
申请号：US12823278
申请日：2010-06-25
申请人： Joel T. Ficke , William E. Hall , Terence B. Hook , Michael A. Sperling , Larry Wissel
发明人： Joel T. Ficke , William E. Hall , Terence B. Hook , Michael A. Sperling , Larry Wissel
IPC分类号： G06F21/73 , H04L9/08
CPC分类号： G06F21/73 , H04L9/08 , H04L9/0866 , H04L9/3278
摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.
摘要翻译：公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。在特定实施例中，电子设备可操作以产生对挑战的响应。电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。电子设备包括被配置为接收挑战的挑战输入。挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

5. 发明申请

US20130256748A1 PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES 有权
标题翻译： FINFET集成电路技术的被动设备
公开(公告)号：US20130256748A1
公开(公告)日：2013-10-03
申请号：US13431414
申请日：2012-03-27
申请人： William F. Clark, JR. , Robert J. Gauthier, JR. , Terence B. Hook , Junjun Li , Theodorus E. Standaert , Thomas A. Wallner
发明人： William F. Clark, JR. , Robert J. Gauthier, JR. , Terence B. Hook , Junjun Li , Theodorus E. Standaert , Thomas A. Wallner
IPC分类号： H01L29/73 , G06F17/50 , H01L21/331
CPC分类号： H01L27/1211 , H01L21/7624 , H01L21/823821 , H01L21/845 , H01L27/0207 , H01L27/0262 , H01L27/0924 , H01L27/1203 , H01L29/66795 , H01L29/785
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。器件区域由轻掺杂的半导体材料组成。器件结构还包括形成在器件区域中并限定结的掺杂区域。器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

6. 发明授权

US08513106B2 Pseudo butted junction structure for back plane connection 有权
公开(公告)号：US08513106B2
公开(公告)日：2013-08-20
申请号：US12964082
申请日：2010-12-09
申请人： Terence B. Hook
发明人： Terence B. Hook
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78648
摘要： Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate.

7. 发明申请

US20120299080A1 STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY 有权
标题翻译：具有多个阈值电压和主动的良好偏置能力的CMOS ETSOI结构
公开(公告)号：US20120299080A1
公开(公告)日：2012-11-29
申请号：US13114283
申请日：2011-05-24
申请人： Robert H. Dennard , Terence B. Hook
发明人： Robert H. Dennard , Terence B. Hook
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823878 , H01L21/823892 , H01L21/84
摘要： A structure includes a semiconductor substrate having a first type of conductivity and a top surface; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer and a plurality of transistor devices disposed upon the semiconductor layer. Each transistor device includes a source, a drain and a gate stack defining a channel between the source and the drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. The structure further includes a well region formed adjacent to the top surface of the substrate and underlying the plurality of transistor devices, the well region having a second type of conductivity and extending to a first depth within the substrate. The structure further includes first isolation regions between adjacent transistor devices and extending through the semiconductor layer to a depth sufficient for electrically isolating the adjacent transistor devices from one another, and second isolation regions between selected adjacent transistor devices. The second isolation regions extend through the silicon layer, through the insulating layer and into the substrate to a second depth that is greater than the first depth to electrically separate the well region into a first well region and a second well region. The structure further includes at least one back gate region disposed wholly within a well region and underlying one of the plurality of transistor devices, the at least one back gate region has the first type of conductivity and is electrically floating within the well region, where during operation the at least one back gate region having the first type of conductivity is biased by leakage and capacitive coupling by a bias potential applied to the well region within which it is disposed.
摘要翻译：一种结构包括具有第一类导电性的半导体衬底和顶表面; 设置在所述顶表面上的绝缘层; 设置在所述绝缘层上的半导体层和设置在所述半导体层上的多个晶体管器件。每个晶体管器件包括源极，漏极和限定在源极和漏极之间的沟道的栅极堆叠，其中一些晶体管器件具有第一类型的沟道导电性，并且剩余的晶体管器件具有第二类型的沟道导电性。所述结构还包括邻近所述衬底的顶表面形成并位于所述多个晶体管器件下方的阱区，所述阱区具有第二类型的导电性并延伸到所述衬底内的第一深度。该结构还包括相邻晶体管器件之间的第一隔离区域，并延伸穿过半导体层至足以将相邻晶体管器件彼此电绝缘的深度以及所选择的相邻晶体管器件之间的第二隔离区域。第二隔离区延伸穿过硅层，穿过绝缘层并进入衬底至比第一深度更大的第二深度，以将阱区电分离成第一阱区和第二阱区。该结构还包括至少一个背栅极区域，其完全设置在阱区域内并且位于多个晶体管器件中的一个之下，所述至少一个背栅极区域具有第一类型的导电性并且在阱区域内电浮动，操作具有第一类型的导电性的至少一个背栅极区域被施加到其所配置的阱区域的偏置电位的泄漏和电容耦合偏置。

8. 发明申请

US20110317829A1 Physically Unclonable Function Implemented Through Threshold Voltage Comparison 失效
标题翻译：通过阈值电压比较实现的物理不可克隆功能
公开(公告)号：US20110317829A1
公开(公告)日：2011-12-29
申请号：US12823278
申请日：2010-06-25
申请人： Joel T. Ficke , William E. Hall , Terence B. Hook , Michael A. Sperling , Larry Wissel
发明人： Joel T. Ficke , William E. Hall , Terence B. Hook , Michael A. Sperling , Larry Wissel
IPC分类号： H04L9/20
CPC分类号： G06F21/73 , H04L9/08 , H04L9/0866 , H04L9/3278
摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.
摘要翻译：公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。在特定实施例中，电子设备可操作以产生对挑战的响应。电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。电子设备包括被配置为接收挑战的挑战输入。挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

9. 发明申请

US20100013026A1 INTEGRATED CIRCUITS COMPRISING RESISTORS HAVING DIFFERENT SHEET RESISTANCES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：包含具有不同表面电阻的电阻的集成电路及其制造方法
公开(公告)号：US20100013026A1
公开(公告)日：2010-01-21
申请号：US12173407
申请日：2008-07-15
申请人： Roger Allen Booth, JR. , Kangguo Cheng , Terence B. Hook
发明人： Roger Allen Booth, JR. , Kangguo Cheng , Terence B. Hook
IPC分类号： H01L27/02 , H01L21/22
CPC分类号： H01L27/0629 , H01L28/20
摘要： The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.
摘要翻译：本文公开了包括具有相同结构但具有不同薄层电阻的电阻器的集成电路的制造。在一个实施例中，一种制造集成电路的方法包括：与半导体衬底之上或之内的第二电阻器横向隔开的第一电阻器同时形成，所述第一和第二电阻器包括掺杂的半导体材料; 在第一和第二电阻器和半导体衬底上沉积掺杂剂接收材料; 在所述第一电阻器上移除所述掺杂剂接收材料，同时将所述掺杂剂接收材料保持在所述第二电阻器上; 以及使所述第一和第二电阻器退火以使所述第一电阻器的第一薄层电阻与所述第二电阻器的第二薄层电阻不同。

10. 发明申请

US20090174008A1 METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING 有权
标题翻译：在发酵加工过程中保护等离子体损伤的FET的方法和结构
公开(公告)号：US20090174008A1
公开(公告)日：2009-07-09
申请号：US11970579
申请日：2008-01-08
申请人： Deleep R. Nair , Terence B. Hook
发明人： Deleep R. Nair , Terence B. Hook
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0266 , H01L29/78
摘要： Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity. The FET-like structure is formed with thinner oxide than the gate oxide of the FET, has a gate structure (poly) connected with the gate of the FET, and may be shorted out by the first metal layer (M1).
摘要翻译：通过在与FET相同的FET中与FET结合并与FET相邻并且具有与阱极性相反的掺杂体，在FEOL处理期间保护FET免受等离子体损伤。 FET型结构形成为具有比FET的栅极氧化物更薄的氧化物，具有与FET的栅极连接的栅极结构（poly），并且可以被第一金属层（M1）短路。

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