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1. 发明授权

US08626480B2 Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors 失效
标题翻译：紧凑型器件/电路/芯片泄漏电流（IDDQ）计算，包括工艺引起的隆起因素
公开(公告)号：US08626480B2
公开(公告)日：2014-01-07
申请号：US12574440
申请日：2009-10-06
申请人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

2. 发明授权

US08237197B2 Asymmetric channel MOSFET 失效
标题翻译：非对称沟道MOSFET
公开(公告)号：US08237197B2
公开(公告)日：2012-08-07
申请号：US12831310
申请日：2010-07-07
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.
摘要翻译：场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

3. 发明申请

US20110227136A1 SPACER PROTECTION AND ELECTRICAL CONNECTION FOR ARRAY DEVICE 失效
标题翻译：阵列保护和电气连接
公开(公告)号：US20110227136A1
公开(公告)日：2011-09-22
申请号：US12728488
申请日：2010-03-22
申请人： Jae-Eun Park , Weipeng Li , Deleep R. Nair , M. Dean Sciacca , Voon-Yew Thean , Ava Wan , Dong-Hun Lee , Yong-Meng Lee
发明人： Jae-Eun Park , Weipeng Li , Deleep R. Nair , M. Dean Sciacca , Voon-Yew Thean , Ava Wan , Dong-Hun Lee , Yong-Meng Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/76895 , H01L29/665 , H01L29/6659
摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
摘要翻译：本公开提供了形成电气装置的方法。该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。源极区和漏极区形成在衬底中。在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。在金属半导体合金上形成层间电介质层。通过金属半导体合金上的层间电介质停止形成通孔。在通孔中的金属半导体合金形成互连。本公开还包括通过上述方法制造的结构。

4. 发明申请

US20070166885A1 Electrode line structure having fine line width and method of forming the same 有权
标题翻译：具有细线宽度的电极线结构及其形成方法
公开(公告)号：US20070166885A1
公开(公告)日：2007-07-19
申请号：US11651322
申请日：2007-01-09
申请人： Joo-won Lee , Kang-soo Chu , Jae-eun Park , Jong-ho Yang
发明人： Joo-won Lee , Kang-soo Chu , Jae-eun Park , Jong-ho Yang
IPC分类号： H01L21/00
CPC分类号： H01L27/10888 , H01L23/5283 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a first line unit, which substantially functions as an electrode line, a second line unit, which has an inclined end in the long axis direction and is separated from the first line unit by a predetermined distance, and an insulating plug, which is interposed between the first line unit and the second line unit and electrically insulates the first line unit from the second line unit.
摘要翻译：在半导体器件的电极线结构及其形成方法中，电极线结构包括半导体衬底和形成在半导体衬底上并在长轴方向上具有倾斜端的电极线。电极线各自包括基本上用作电极线的第一线单元，在长轴方向上具有倾斜端并与第一线单元隔开预定距离的第二线单元，以及绝缘插头，其插入在第一线路单元和第二线路单元之间，并且将第一线路单元与第二线路单元电绝缘。

5. 发明授权

US06858533B2 Semiconductor device having an etch stopper formed of a sin layer by low temperature ALD and method of fabricating the same 有权
标题翻译：具有通过低温ALD由sin层形成的蚀刻停止件的半导体器件及其制造方法
公开(公告)号：US06858533B2
公开(公告)日：2005-02-22
申请号：US10612028
申请日：2003-07-02
申请人： Kang-soo Chu , J o-won Lee , Jae-eun Park , Jong-ho Yang
发明人： Kang-soo Chu , J o-won Lee , Jae-eun Park , Jong-ho Yang
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/311 , H01L21/318 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/31111 , H01L21/31116
摘要： Provided are a semiconductor device having an etch stopper formed of a nitride film by low temperature atomic layer deposition which can prevent damage to a semiconductor substrate and a method for fabricating the semiconductor device. Damage to the semiconductor substrate under the etch stopper composed of a second nitride film can be prevented by forming a first nitride film using high temperature LPCVD on the semiconductor substrate, forming the etch stopper including the second nitride film by low temperature ALD on the first nitride film, and removing the second nitride film by dry etching, thus taking advantage of the different etch selectivities of the first nitride film and the second nitride film.
摘要翻译：提供一种半导体器件，其具有通过低温原子层沉积由氮化物膜形成的蚀刻停止物，其能够防止对半导体衬底的损坏以及制造半导体器件的方法。通过在半导体衬底上形成使用高温LPCVD的第一氮化物膜，可以防止在由第二氮化物膜构成的蚀刻停止器下的半导体衬底的损伤，通过第一氮化物上的低温ALD形成包括第二氮化物膜的蚀刻停止层膜，并通过干蚀刻去除第二氮化物膜，从而利用第一氮化物膜和第二氮化物膜的不同蚀刻选择性。

6. 发明授权

US08563394B2 Integrated circuit structure having substantially planar N-P step height and methods of forming 失效
标题翻译：具有基本上平面的N-P台阶高度的集成电路结构和形成方法
公开(公告)号：US08563394B2
公开(公告)日：2013-10-22
申请号：US13083631
申请日：2011-04-11
申请人： Weipeng Li , Deleep R. Nair , Jae-Eun Park , Voon-Yew Thean , Young Way Teh
发明人： Weipeng Li , Deleep R. Nair , Jae-Eun Park , Voon-Yew Thean , Young Way Teh
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76232 , H01L21/823807
摘要： Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
摘要翻译：公开了用于形成具有基本平坦的N-P台阶高度的集成电路结构的解决方案。在一个实施例中，一种方法包括：提供具有n型场效应晶体管（NFET）区域和p型场效应晶体管（PFET）区域的结构; 在PFET区域上形成掩模以使NFET区域露出; 在暴露的NFET区域上进行稀释的氟化氢（DHF）清洁以显着降低NFET区域的STI分布; 以及在执行DHF之后在PFET区域中形成硅锗（SiGE）通道。

7. 发明授权

US07521308B2 Dual layer stress liner for MOSFETS 失效
标题翻译：用于MOSFET的双层应力衬垫
公开(公告)号：US07521308B2
公开(公告)日：2009-04-21
申请号：US11616147
申请日：2006-12-26
申请人： Deleep R. Nair , Christopher V. Baiocco , Xiangdong Chen , Junjung Kim , Jae-eun Park , Daewon Yang
发明人： Deleep R. Nair , Christopher V. Baiocco , Xiangdong Chen , Junjung Kim , Jae-eun Park , Daewon Yang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/31604 , H01L29/66575
摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.
摘要翻译：制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。栅极结构和导体区域构成晶体管。为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。第二功率电平比第一功率电平高（例如，至少高5倍）。

8. 发明授权

US07510969B2 Electrode line structure having fine line width and method of forming the same 有权
标题翻译：具有细线宽度的电极线结构及其形成方法
公开(公告)号：US07510969B2
公开(公告)日：2009-03-31
申请号：US11651322
申请日：2007-01-09
申请人： Joo-won Lee , Kang-soo Chu , Jae-eun Park , Jong-ho Yang
发明人： Joo-won Lee , Kang-soo Chu , Jae-eun Park , Jong-ho Yang
IPC分类号： H01L21/44
CPC分类号： H01L27/10888 , H01L23/5283 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a first line unit, which substantially functions as an electrode line, a second line unit, which has an inclined end in the long axis direction and is separated from the first line unit by a predetermined distance, and an insulating plug, which is interposed between the first line unit and the second line unit and electrically insulates the first line unit from the second line unit.
摘要翻译：在半导体器件的电极线结构及其形成方法中，电极线结构包括半导体衬底和形成在半导体衬底上并在长轴方向上具有倾斜端的电极线。电极线各自包括基本上用作电极线的第一线单元，在长轴方向上具有倾斜端并与第一线单元隔开预定距离的第二线单元，以及绝缘插头，其插入在第一线路单元和第二线路单元之间，并且将第一线路单元与第二线路单元电绝缘。

9. 发明申请

US20060040510A1 Semiconductor device with silicon dioxide layers formed using atomic layer deposition 审中-公开
标题翻译：使用原子层沉积形成二氧化硅层的半导体器件
公开(公告)号：US20060040510A1
公开(公告)日：2006-02-23
申请号：US11225999
申请日：2005-09-14
申请人： Joo-won Lee , Jae-eun Park , Jong-ho Yang , Kang-soo Chu
发明人： Joo-won Lee , Jae-eun Park , Jong-ho Yang , Kang-soo Chu
IPC分类号： H01L21/31
CPC分类号： H01L21/31612 , C23C16/402 , C23C16/45534 , C23C16/56 , H01L21/02164 , H01L21/02208 , H01L21/02277 , H01L21/0228 , H01L21/02337 , H01L21/0234 , H01L21/3122 , H01L21/3141
摘要： Improved methods are disclosed for catalyst-assisted atomic layer deposition (ALD) to form a silicon dioxide layer having superior properties on a semiconductor substrate by using a first reactant component consisting of a silicon compound having at least two silicon atoms, or using a tertiary aliphatic amine as the catalyst component, or both in combination, together with related purging methods and sequencing.
摘要翻译：公开了用于催化剂辅助原子层沉积（ALD）的改进方法，以通过使用由具有至少两个硅原子的硅化合物组成的第一反应物组分或使用叔脂族基团形成在半导体衬底上具有优异性能的二氧化硅层胺作为催化剂组分，或两者结合，以及相关的清洗方法和测序。

10. 发明申请

US20050233598A1 Method of fabricating high-k dielectric layer having reduced impurity 有权
标题翻译：制造具有减少的杂质的高k电介质层的方法
公开(公告)号：US20050233598A1
公开(公告)日：2005-10-20
申请号：US11107559
申请日：2005-04-15
申请人： Hyung-Suk Jung , Jong-Ho Lee , Ha-Jin Lim , Jae-Eun Park , Yun-Seok Kim , Jong-Ho Yang
发明人： Hyung-Suk Jung , Jong-Ho Lee , Ha-Jin Lim , Jae-Eun Park , Yun-Seok Kim , Jong-Ho Yang
IPC分类号： H01L21/31 , C23C16/40 , H01L21/28 , H01L21/314 , H01L21/336 , H01L21/469 , H01L29/51
CPC分类号： H01L21/022 , C23C16/402 , C23C16/45525 , C23C16/45527 , C23C16/45529 , H01L21/0228 , H01L21/02318 , H01L21/28185 , H01L21/28194 , H01L21/3142 , H01L21/3143 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.
摘要翻译：公开了制造用于半导体应用的具有减少的杂质的高k电介质层的方法。该方法包括以下步骤：结合对叠层电介质层执行的后处理步骤，使用ALD法形成具有形成在半导体衬底上的第一电介质层和第二电介质层的叠层电介质层。形成堆叠的电介质层并进行后处理的步骤至少重复一次，从而制造高k电介质层。

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