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1. 发明申请

US20230037321A1 METHOD AND APPARATUS FOR VECTOR SORTING USING VECTOR PERMUTATION LOGIC 有权
公开(公告)号：US20230037321A1
公开(公告)日：2023-02-09
申请号：US17958503
申请日：2022-10-03
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Timothy David Anderson , Mujibur Rahman
IPC分类号： G06F9/30 , G06F17/16 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/38 , G06F7/57 , G06F9/48
摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

2. 发明授权

US11461096B2 Method and apparatus for vector sorting using vector permutation logic 有权
公开(公告)号：US11461096B2
公开(公告)日：2022-10-04
申请号：US16589126
申请日：2019-09-30
申请人： Texas Instruments Incorporated
发明人： Timothy David Anderson , Mujibur Rahman
IPC分类号： G06F9/22 , G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

3. 发明申请

US20220156073A1 METHOD AND APPARATUS TO SORT A VECTOR FOR A BITONIC SORTING ALGORITHM 有权
公开(公告)号：US20220156073A1
公开(公告)日：2022-05-19
申请号：US17665958
申请日：2022-02-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Timothy David Anderson , Mujibur Rahman
IPC分类号： G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
摘要： A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

4. 发明授权

US11327761B2 Processing device with vector transformation execution 有权
公开(公告)号：US11327761B2
公开(公告)日：2022-05-10
申请号：US16881327
申请日：2020-05-22
申请人： Texas Instruments Incorporated
发明人： Mujibur Rahman , Timothy David Anderson , Joseph Zbiciak
IPC分类号： G06F9/30 , G06F9/38
摘要： An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.

5. 发明授权

US11301248B2 Method and apparatus for dual multiplication units in a data path 有权
公开(公告)号：US11301248B2
公开(公告)日：2022-04-12
申请号：US16878603
申请日：2020-05-20
申请人： Texas Instruments Incorporated
发明人： Mujibur Rahman , Timothy David Anderson , Soujanya Narnur
IPC分类号： G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
摘要： A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

6. 发明授权

US11281464B2 Method and apparatus to sort a vector for a bitonic sorting algorithm 有权
公开(公告)号：US11281464B2
公开(公告)日：2022-03-22
申请号：US16589133
申请日：2019-09-30
申请人： Texas Instruments Incorporated
发明人： Timothy David Anderson , Mujibur Rahman
IPC分类号： G06F9/30 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/38 , G06F17/16 , H03H17/06 , G06F9/48
摘要： A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

7. 发明申请

US20210357218A1 METHOD AND APPARATUS FOR VECTOR SORTING 有权
公开(公告)号：US20210357218A1
公开(公告)日：2021-11-18
申请号：US17387260
申请日：2021-07-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Timothy David Anderson , Mujibur Rahman
IPC分类号： G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

8. 发明授权

US09448767B2 Three-term predictive adder and/or subtracter 有权
标题翻译：三项预测加法器和/或减法器
公开(公告)号：US09448767B2
公开(公告)日：2016-09-20
申请号：US14192102
申请日：2014-02-27
申请人： Texas Instruments Incorporated
发明人： Timothy D. Anderson , Mujibur Rahman , Kai Chirca
IPC分类号： G06F7/50 , G06F7/57 , G06F7/505 , G06F7/506
CPC分类号： G06F7/57 , G06F7/5055 , G06F7/506
摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.
摘要翻译：预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分的位数在电位和。预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

9. 发明申请

US20150154024A1 Vector SIMD VLIW Data Path Architecture 审中-公开
标题翻译：矢量SIMD VLIW数据路径架构
公开(公告)号：US20150154024A1
公开(公告)日：2015-06-04
申请号：US14327084
申请日：2014-07-09
申请人： Texas Instruments Incorporated
发明人： Timothy David Anderson , Duc Quang Bui , Mujibur Rahman , Joseph Raymond Michael Zbiciak , Eric Biscondi , Peter Dent , Jelena Milanovic , Ashish Shrivastava
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30112 , G06F9/3893
摘要： A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
摘要翻译：特别适用于各种操作数宽度和数据大小的单指令多数据（SIMD）操作的超长指令字（VLIW）数字信号处理器。向量比较指令比较第一和第二操作数并存储比较位。伴随向量条件指令根据相应谓词数据寄存器位的状态执行条件操作。谓词单元对包括一元操作和二进制操作的至少一个谓词数据寄存器中的数据执行数据处理操作。谓词单元还可以在通用数据寄存器文件和谓词数据寄存器文件之间传送数据。

10. 发明申请

US20140181165A1 Three-Term Predictive Adder and/or Subtracter 审中-公开
标题翻译：三阶预测加法器和/或减法器
公开(公告)号：US20140181165A1
公开(公告)日：2014-06-26
申请号：US14192102
申请日：2014-02-27
申请人： Texas Instruments Incorporated
发明人： Timothy D. Anderson , Mujibur Rahman , Kai Chirca
IPC分类号： G06F7/57
CPC分类号： G06F7/57 , G06F7/5055 , G06F7/506
摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.
摘要翻译：预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示波纹部分的位数在电位和。预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

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