专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07602274B2 Dynamic configuration of a radio frequency transponder 有权
标题翻译：射频应答器的动态配置
公开(公告)号：US07602274B2
公开(公告)日：2009-10-13
申请号：US11079719
申请日：2005-03-14
申请人： Thomas Youbok Lee , James B. Nolan , Steve Vernier , Ruan Lourens , Vivien Delport , Alan Lamphier , Glen Allen Sullivan
发明人： Thomas Youbok Lee , James B. Nolan , Steve Vernier , Ruan Lourens , Vivien Delport , Alan Lamphier , Glen Allen Sullivan
IPC分类号： H04Q5/22 , G05B19/00 , G06F7/04 , H04B1/00
CPC分类号： G06K19/0723 , G06K19/0726 , G06K19/07767
摘要： A multi-channel remote keyless entry (RKE) transponder having dynamically re-configurable input channel selection, channel disable, settable sensitivity for each channel, wake-up filter timing parameters, automatic gain control hold, internal tuning capacitor selection for each channel's antenna, minimum modulation depth requirement for input signal and bi-directional talk-back. Programmable minimum modulation depth requirement reduces false wake-up of the RKE transponder. An antenna for each channel of the RKE transponder may be tuned with internal tuning capacitors for improved range and receiver sensitivity. The internal tuning capacitor parameters may be stored in a configuration register. Gain of the channel may be fixed while the antenna is tuned. The antennas may be de-queued for talk-back to a base station for low frequency bi-directional communications. An external control device may dynamically read from and write to the configuration registers via a serial communications interface.
摘要翻译：具有动态可重配置的输入通道选择，通道禁用，每个通道的可设置灵敏度，唤醒滤波器定时参数，自动增益控制保持，每个通道天线的内部调谐电容选择的多通道遥控无钥匙进入（RKE）输入信号和双向对讲的最小调制深度要求。可编程的最小调制深度要求可减少RKE转发器的假唤醒。可以使用内部调谐电容器调整RKE应答器的每个通道的天线，以提高范围和接收机灵敏度。内部调谐电容参数可以存储在配置寄存器中。天线调谐时，通道的增益可能会固定。天线可以被排队，用于与基站通话用于低频双向通信。外部控制设备可以通过串行通信接口动态地读取和写入配置寄存器。

2. 发明申请

US20050237163A1 Dynamic configuration of a radio frequency transponder 有权
标题翻译：射频应答器的动态配置
公开(公告)号：US20050237163A1
公开(公告)日：2005-10-27
申请号：US11079719
申请日：2005-03-14
申请人： Thomas Lee , James Nolan , Steve Vernier , Ruan Lourens , Vivien Delport , Alan Lamphier , Glen Sullivan
发明人： Thomas Lee , James Nolan , Steve Vernier , Ruan Lourens , Vivien Delport , Alan Lamphier , Glen Sullivan
IPC分类号： G06K19/07 , G07C9/00 , H04Q5/22
CPC分类号： G06K19/0723 , G06K19/0726 , G06K19/07767
摘要： A multi-channel remote keyless entry (RKE) transponder having dynamically re-configurable input channel selection, channel disable, settable sensitivity for each channel, wake-up filter timing parameters, automatic gain control hold, internal tuning capacitor selection for each channel's antenna, minimum modulation depth requirement for input signal and bi-directional talk-back. Programmable minimum modulation depth requirement reduces false wake-up of the RKE transponder. An antenna for each channel of the RKE transponder may be tuned with internal tuning capacitors for improved range and receiver sensitivity. The internal tuning capacitor parameters may be stored in a configuration register. Gain of the channel may be fixed while the antenna is tuned. The antennas may be de-queued for talk-back to a base station for low frequency bi-directional communications. An external control device may dynamically read from and write to the configuration registers via a serial communications interface.
摘要翻译：具有动态可重配置的输入通道选择，通道禁用，每个通道的可设置灵敏度，唤醒滤波器定时参数，自动增益控制保持，每个通道天线的内部调谐电容选择的多通道遥控无钥匙进入（RKE）输入信号和双向对讲的最小调制深度要求。可编程的最小调制深度要求可减少RKE转发器的假唤醒。可以使用内部调谐电容器调整RKE应答器的每个通道的天线，以提高范围和接收机灵敏度。内部调谐电容参数可以存储在配置寄存器中。天线调谐时，通道的增益可能会固定。天线可以被排队，用于与基站通话用于低频双向通信。外部控制设备可以通过串行通信接口动态地读取和写入配置寄存器。

3. 发明授权

US07800250B2 Connection of an internal regulator to an external filter/stabilization capacitor through a selectable external connection and prevention of a current surge therebetween 有权
标题翻译：通过可选择的外部连接将内部稳压器连接到外部滤波器/稳定电容器，并防止其间的电流浪涌
公开(公告)号：US07800250B2
公开(公告)日：2010-09-21
申请号：US12107531
申请日：2008-04-22
申请人： Richard Hull , Vivien Delport , Zacharias Marthinus Smit , Sean Steedman , Jerrold S. Zdenek , Michael Charles , Ruan Lourens
发明人： Richard Hull , Vivien Delport , Zacharias Marthinus Smit , Sean Steedman , Jerrold S. Zdenek , Michael Charles , Ruan Lourens
IPC分类号： H01H47/02
CPC分类号： G11C5/147 , Y10T307/74 , Y10T307/747 , Y10T307/858
摘要： An integrated circuit device provides a choice of external pins (connections) that may be user selectable for coupling an external filter/stabilization capacitor to an internal voltage regulator. However, connecting the output of a internal voltage regulator to an uncharged external filter/stabilization capacitor (or to a capacitor charged to a different voltage level than the internal regulation voltage) through a low impedance path can cause the regulator output voltage to sag/spike if the internal voltage regulator tries to charge/discharge the capacitor up/down to equilibrium with the regulator output voltage. To minimize this potential sag/spike, the voltage on the external filter/stabilization capacitor may be adjusted in a controlled manner to substantially the same voltage as the voltage on the output of the internal voltage regulator, and then the internal voltage regulator is operationally coupled through a low impedance to the external regulator filter/stabilization capacitor.
摘要翻译：集成电路器件提供可选择用于将外部滤波器/稳定电容器耦合到内部稳压器的外部引脚（连接）的选择。然而，通过低阻抗路径将内部稳压器的输出连接到不带电的外部滤波器/稳定电容器（或者与内部调节电压相比，被充电到不同电压电平的电容器）可能会导致稳压器输出电压下垂/尖峰如果内部电压调节器试图将电容器上/下放电到稳压器输出电压的平衡。为了最小化该潜在的下垂/尖峰，可以以受控的方式将外部滤波器/稳定电容器上的电压调节到与内部电压调节器的输出端上的电压基本相同的电压，然后内部电压调节器可操作地耦合通过低阻抗到外部调节滤波器/稳定电容器。

4. 发明申请

US20080273391A1 Regulator Bypass Start-Up in an Integrated Circuit Device 审中-公开
标题翻译：集成电路设备中的调节器旁路启动
公开(公告)号：US20080273391A1
公开(公告)日：2008-11-06
申请号：US12102400
申请日：2008-04-14
申请人： Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ruan Lourens , Michael Charles , Joseph Julicher , Eric Schroeder
发明人： Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ruan Lourens , Michael Charles , Joseph Julicher , Eric Schroeder
IPC分类号： G11C5/14 , G11C11/34
CPC分类号： G11C5/147
摘要： An internal voltage regulator in an integrated circuit device is always active upon initial start-up and/or power-on-reset operations. The internal voltage regulator protects the low voltage core logic circuits of the integrated circuit device from excessively high voltages that may be present in a particular application. In addition, nonvolatile memory may be part of and operational with the low voltage core logic circuits for storing device operating parameters. Therefore, the internal voltage regulator also protects the low voltage nonvolatile memory from excessive high voltages. Once the integrated circuit device has stabilized and all logic circuits therein are fully function, a bit(s) in the nonvolatile memory may be read to determine if the internal voltage regulator should remain active, e.g., how power operation with a high voltage source, or be placed into a bypass mode for low power operation when the integrated circuit device is powered by a low voltage.
摘要翻译：初始启动和/或上电复位操作时，集成电路器件中的内部稳压器始终有效。内部电压调节器保护集成电路器件的低电压核心逻辑电路免受可能存在于特定应用中的过高的电压。此外，非易失性存储器可以是用于存储设备操作参数的低压核心逻辑电路的一部分并且可操作。因此，内部稳压器也可以保护低压非易失性存储器免受过高的高压。一旦集成电路器件已经稳定并且其中的所有逻辑电路都完全功能，则可以读取非易失性存储器中的位以确定内部电压调节器是否应保持有效，例如，如何使用高电压源进行功率操作，或者当集成电路器件由低电压供电时，将其置于旁路模式以进行低功耗操作。

5. 发明申请

US20100188014A1 MODULATOR MODULE IN AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：集成电路设备中的调制器模块
公开(公告)号：US20100188014A1
公开(公告)日：2010-07-29
申请号：US12690258
申请日：2010-01-20
申请人： Zeke R. Lundstrum , Keith Curtis , Sean Steedman , Vivien Delport , Jerrold S. Zdenek
发明人： Zeke R. Lundstrum , Keith Curtis , Sean Steedman , Vivien Delport , Jerrold S. Zdenek
IPC分类号： H05B41/36 , H03C1/00 , H03C3/00
CPC分类号： H03C3/00 , H04L27/122 , H05B41/2828
摘要： An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.
摘要翻译：集成电路装置具有调制器模块，该调制器模块提供包括基于调制器信号选择的一个频率键控开关或交替的两个或多个不同频率或相位之间的调制信号。可以从多个频率源中选择一个或多个频率或相位。将一个频率开启或关闭，或者在至少两个不同频率或相位之间切换可以与两个或更多个不同频率或相位中的一个或两个同步，使得“毛刺”或杂散不被引入到调制信号中。集成电路设备还可以包括处理器，存储器，数字逻辑和输入 - 输出。频率源可能在数字设备内部或外部。调制器信号可以包括从数字设备的数字逻辑和/或处理器产生的串行数据。

6. 发明申请

US20090144511A1 Enhanced Microprocessor or Microcontroller 有权
标题翻译：增强微处理器或微控制器
公开(公告)号：US20090144511A1
公开(公告)日：2009-06-04
申请号：US12147647
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/35
摘要： An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.
摘要翻译： n位微处理器设备具有n位中央处理单元（CPU）; 多个特殊功能寄存器和通用寄存器，其被存储器映射到多个存储体，具有至少两个16位间接存储器地址寄存器，这些存储器地址寄存器可由所有存储体中的CPU访问; 用于将CPU与多个存储体中的一个耦合的存储单元存取单元; 与CPU耦合的数据存储器; 以及与CPU耦合的程序存储器，其中间接地址寄存器可操作以访问数据存储器或程序存储器，并且其中每个间接存储器地址寄存器中的位指示对数据存储器或程序存储器的访问。

7. 发明授权

US08539210B2 Context switching with automatic saving of special function registers memory-mapped to all banks 有权
标题翻译：具有自动保存特殊功能寄存器的上下文切换，内存映射到所有存储区
公开(公告)号：US08539210B2
公开(公告)日：2013-09-17
申请号：US12147746
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F9/48
CPC分类号： G06F9/461
摘要： A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.
摘要翻译：微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以被存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

8. 发明申请

US20130064372A1 CODE HOPPING BASED SYSTEM WITH INCREASED SECURITY 有权
标题翻译：基于HOPPING的系统具有增强的安全性
公开(公告)号：US20130064372A1
公开(公告)日：2013-03-14
申请号：US13610377
申请日：2012-09-11
申请人： Vivien Delport , Michael A. Stuckey , Enrique Aleman
发明人： Vivien Delport , Michael A. Stuckey , Enrique Aleman
IPC分类号： H04L9/28 , H04W12/00
CPC分类号： E05F15/60 , E05D15/0652 , E05D15/38 , E05F15/00 , E05F15/603 , E05F15/684 , E05F15/70 , E05F15/77 , E05Y2201/656 , E05Y2201/668 , E05Y2201/672 , E05Y2900/106 , F16B7/0413 , F16B7/042 , F16B7/0433 , G07C9/00015 , G07C9/00309 , G07C9/00857 , G07C9/00896 , G07C2009/00412 , G07C2009/00769 , G07C2009/00888 , G07C2009/00928 , Y10T16/379 , Y10T29/49959
摘要： An access system includes a transmitter and a receiver for exchange of secure data wherein the system uses an encryption and a decryption algorithm to exchange a secure data packet. The secure data packet may include an unencrypted data packet and an encrypted data packet. The encrypted data packet may include first data encrypted by the encryption algorithm, and data decrypted by the decryption algorithm, wherein the data decrypted by the decryption algorithm includes a combination of a secure signature and second data encrypted by the encryption algorithm.
摘要翻译：访问系统包括用于交换安全数据的发送器和接收器，其中系统使用加密和解密算法来交换安全数据包。安全数据分组可以包括未加密的数据分组和加密的数据分组。加密数据分组可以包括由加密算法加密的第一数据和由解密算法解密的数据，其中由解密算法解密的数据包括由加密算法加密的安全签名和第二数据的组合。

9. 发明申请

US20110234417A1 FAILSAFE OSCILLATOR MONITOR AND ALARM 有权
标题翻译：失效振荡器监测和报警
公开(公告)号：US20110234417A1
公开(公告)日：2011-09-29
申请号：US12732595
申请日：2010-03-26
申请人： Enrique Aleman , Jonathan Dillon , Vivien Delport , Joseph Julicher
发明人： Enrique Aleman , Jonathan Dillon , Vivien Delport , Joseph Julicher
IPC分类号： G08B21/00 , H03K3/02
CPC分类号： G06F1/14 , G01R19/16585 , H03B5/36
摘要： A failsafe oscillator monitor and alarm circuit receives clock pulses from an external oscillator that if a failure thereto occurs, the failsafe oscillator monitor and alarm circuit will notify a digital processor of the external oscillator failure. The failsafe oscillator monitor and alarm circuit is a very low current usage circuit that charges a storage capacitor with clock pulses from the external oscillator when functioning normally and discharges the storage capacitor with a constant current sink if the external oscillator stops functioning. When the voltage charge on the storage capacitor becomes less than a reference voltage an alarm signal is sent to the digital processor for exception or error handling of the failed external oscillator.
摘要翻译：故障安全振荡器监视和报警电路接收来自外部振荡器的时钟脉冲，如果发生故障，故障保护振荡器监视和报警电路将通知数字处理器外部振荡器故障。故障安全振荡器监视和报警电路是一个非常低的电流使用电路，当正常工作时，外部振荡器的时钟脉冲对存储电容充电，如果外部振荡器停止工作，则使用恒定电流吸收器对存储电容器进行放电。当存储电容器上的电压电压变得小于参考电压时，报警信号被发送到数字处理器以用于故障外部振荡器的异常或错误处理。

10. 发明授权

US07996647B2 Enhanced microprocessor or microcontroller 有权
标题翻译：增强的微处理器或微控制器
公开(公告)号：US07996647B2
公开(公告)日：2011-08-09
申请号：US12178249
申请日：2008-07-23
申请人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
发明人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
IPC分类号： G06F12/02
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30138 , G06F9/342 , G06F12/06
摘要： A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.
摘要翻译：处理器设备具有具有线性地址空间的数据存储器，数据存储器可通过多个存储体访问。存储体的至少一个子集被组织成使得子集的每个存储体具有至少第一和第二存储区，其中由多个连续存储体的第二存储区形成连续存储块。提供地址调整单元，当使用预定义的地址范围时，将预定义地址范围内的地址转换为访问所述第二存储区域，使得通过该地址，多个第二存储区域形成连续线性存储器块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式