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1. 发明授权

US09450585B2 Selecting four signals from sixteen inputs 有权
标题翻译：从十六个输入中选择四个信号
公开(公告)号：US09450585B2
公开(公告)日：2016-09-20
申请号：US13449687
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17744
摘要： An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.
摘要翻译：一种用于从设备中的多个y信号中选择多个输入信号的装置具有具有多个n至1个多路复用器的交换矩阵，其中每个n至1多路复用器被分配给y信号的n个的不同输入集合其中n至1个多路复用器中的每一个的每组输入信号的小于n个输入信号的子集也是另一n到1个多路复用器的输入信号的子集。

2. 发明授权

US08793426B2 Microcontroller with linear memory access in a banked memory 有权
标题翻译：具有线性存储器存取存储器的微控制器
公开(公告)号：US08793426B2
公开(公告)日：2014-07-29
申请号：US12701664
申请日：2010-02-08
申请人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
发明人： Zeke R. Lundstrum , Vivien Delport , Sean Steedman , Joseph Julicher
IPC分类号： G06F12/00
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.
摘要翻译：微控制器具有分成多个存储体的数据存储器，用于向数据存储器提供地址的地址多路复用器，向地址多路复用器的第一输入端提供第一部分地址的指令寄存器，不是地址复用器的存储体选择寄存器映射到数据存储器，用于向地址多路复用器的第一输入提供第二部分地址，以及映射到数据存储器的多个特殊功能寄存器，其中多个特殊功能寄存器包括与第二个地址多路复用器的输入，并且其中数据存储器包括多个存储器组中的多于一个存储器组，其形成没有映射特殊功能寄存器的线性数据存储器块。

3. 发明授权

US08710863B2 Configurable logic cells 有权
标题翻译：可配置的逻辑单元
公开(公告)号：US08710863B2
公开(公告)日：2014-04-29
申请号：US13449993
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F15/7871 , H03K19/177 , H03K19/17708
摘要： A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.
摘要翻译：处理器包括一个RISC CPU内核; 以及包括一个或多个可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为允许实时软件访问处理器的内部配置和信号路径。可配置逻辑单元外设可能具有实时配置控制。

4. 发明授权

US08373357B2 Modulator module in an integrated circuit device 有权
标题翻译：集成电路设备中的调制器模块
公开(公告)号：US08373357B2
公开(公告)日：2013-02-12
申请号：US12690258
申请日：2010-01-20
申请人： Zeke R. Lundstrum , Keith Curtis , Sean Steedman , Vivien Delport , Jerrold S. Zdenek
发明人： Zeke R. Lundstrum , Keith Curtis , Sean Steedman , Vivien Delport , Jerrold S. Zdenek
IPC分类号： H05B37/02 , H03C3/00
CPC分类号： H03C3/00 , H04L27/122 , H05B41/2828
摘要： An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.
摘要翻译：集成电路装置具有调制器模块，该调制器模块提供包括基于调制器信号选择的一个频率键控开关或交替的两个或多个不同频率或相位之间的调制信号。可以从多个频率源中选择一个或多个频率或相位。将一个频率开启或关闭，或者在至少两个不同的频率或相位之间切换可以与两个或多个不同的频率或相位中的一个或两个同步，使得毛刺或杂散不被引入到调制信号中。集成电路设备还可以包括处理器，存储器，数字逻辑和输入 - 输出。频率源可能在数字设备内部或外部。调制器信号可以包括从数字设备的数字逻辑和/或处理器产生的串行数据。

5. 发明申请

US20120271968A1 LOGIC DEVICE FOR COMBINING VARIOUS INTERRUPT SOURCES INTO A SINGLE INTERRUPT SOURCE AND VARIOUS SIGNAL SOURCES TO CONTROL DRIVE STRENGTH 审中-公开
标题翻译：用于将各种中断源组合到单个中断源和各种信号源以控制驱动强度的逻辑设备
公开(公告)号：US20120271968A1
公开(公告)日：2012-10-25
申请号：US13450079
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： G06F13/14
CPC分类号： H03K19/17712 , H03K19/17708
摘要： A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions.
摘要翻译：处理器包括RISC CPU内核和包括可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为将多个输入组合成单个输出。可配置逻辑单元可以被编程为用作多个预定逻辑功能之一。

6. 发明申请

US20100023671A1 Enhanced Microprocessor or Microcontroller 有权
标题翻译：增强微处理器或微控制器
公开(公告)号：US20100023671A1
公开(公告)日：2010-01-28
申请号：US12178249
申请日：2008-07-23
申请人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
发明人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
IPC分类号： G06F12/02
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30138 , G06F9/342 , G06F12/06
摘要： A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.
摘要翻译：处理器设备具有具有线性地址空间的数据存储器，数据存储器可通过多个存储体访问。存储体的至少一个子集被组织成使得子集的每个存储体具有至少第一和第二存储区，其中由多个连续存储体的第二存储区形成连续存储块。提供地址调整单元，当使用预定义的地址范围时，将预定义地址范围内的地址转换为访问所述第二存储区域，使得通过该地址，多个第二存储区域形成连续线性存储器块。

7. 发明授权

US07589568B2 Variable power and response time brown-out-reset circuit 有权
标题翻译：可变功率和响应时间欠压复位电路
公开(公告)号：US07589568B2
公开(公告)日：2009-09-15
申请号：US11744365
申请日：2007-05-04
申请人： Sean Steedman , Ruan Lourens , Richard Hull
发明人： Sean Steedman , Ruan Lourens , Richard Hull
IPC分类号： H03K5/22
CPC分类号： H03K17/22 , G01R19/16552 , G06F1/24 , G06F1/30 , H03K2217/0036
摘要： A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.
摘要翻译：具有可编程功率和响应时间特性的欠压复位电路。这些特性可以通过n位宽的总线编程，用于2n种不同的特性，从非常低的功耗和较慢的响应时间到非常快的响应时间和更高的功耗。可以使用串行一线总线来代替n位宽的总线。

8. 发明申请

US20080273391A1 Regulator Bypass Start-Up in an Integrated Circuit Device 审中-公开
标题翻译：集成电路设备中的调节器旁路启动
公开(公告)号：US20080273391A1
公开(公告)日：2008-11-06
申请号：US12102400
申请日：2008-04-14
申请人： Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ruan Lourens , Michael Charles , Joseph Julicher , Eric Schroeder
发明人： Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ruan Lourens , Michael Charles , Joseph Julicher , Eric Schroeder
IPC分类号： G11C5/14 , G11C11/34
CPC分类号： G11C5/147
摘要： An internal voltage regulator in an integrated circuit device is always active upon initial start-up and/or power-on-reset operations. The internal voltage regulator protects the low voltage core logic circuits of the integrated circuit device from excessively high voltages that may be present in a particular application. In addition, nonvolatile memory may be part of and operational with the low voltage core logic circuits for storing device operating parameters. Therefore, the internal voltage regulator also protects the low voltage nonvolatile memory from excessive high voltages. Once the integrated circuit device has stabilized and all logic circuits therein are fully function, a bit(s) in the nonvolatile memory may be read to determine if the internal voltage regulator should remain active, e.g., how power operation with a high voltage source, or be placed into a bypass mode for low power operation when the integrated circuit device is powered by a low voltage.
摘要翻译：初始启动和/或上电复位操作时，集成电路器件中的内部稳压器始终有效。内部电压调节器保护集成电路器件的低电压核心逻辑电路免受可能存在于特定应用中的过高的电压。此外，非易失性存储器可以是用于存储设备操作参数的低压核心逻辑电路的一部分并且可操作。因此，内部稳压器也可以保护低压非易失性存储器免受过高的高压。一旦集成电路器件已经稳定并且其中的所有逻辑电路都完全功能，则可以读取非易失性存储器中的位以确定内部电压调节器是否应保持有效，例如，如何使用高电压源进行功率操作，或者当集成电路器件由低电压供电时，将其置于旁路模式以进行低功耗操作。

9. 发明授权

US08539210B2 Context switching with automatic saving of special function registers memory-mapped to all banks 有权
标题翻译：具有自动保存特殊功能寄存器的上下文切换，内存映射到所有存储区
公开(公告)号：US08539210B2
公开(公告)日：2013-09-17
申请号：US12147746
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F9/48
CPC分类号： G06F9/461
摘要： A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.
摘要翻译：微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以被存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

10. 发明授权

US08154317B2 Integrated circuit device to support inductive sensing 有权
标题翻译：集成电路器件支持感应感应
公开(公告)号：US08154317B2
公开(公告)日：2012-04-10
申请号：US12560855
申请日：2009-09-16
申请人： Sean Steedman , Keith E. Curtis , Radu Ruscu , Petru Cristian Pop
发明人： Sean Steedman , Keith E. Curtis , Radu Ruscu , Petru Cristian Pop
IPC分类号： G01R31/26 , G01R31/3187
CPC分类号： H03K17/96 , H03K2217/96038
摘要： An integrated circuit device inductive touch analog front end (AFE) excites selected ones of a plurality of inductive touch sensors, measures voltages across the coils of the plurality of inductive touch sensors, and provides analog output signals representative of these coil voltages. A physical displacement (touch) to the inductive sensor causes the inductance value of the inductive touch sensor to change with a corresponding change in a voltage across the coil of the inductive touch sensor. A digital processor controls selection of each one of the plurality of inductive touch sensors and receives the respective analog output voltage signal from the inductive touch AFE. When a sufficient change in the coil voltage is determined by the digital processor, that inductive touch sensor is assumed to have been actuated and the digital processor takes action based upon which one of the plurality of inductive touch sensors was actuated (touched).
摘要翻译：集成电路装置感应式模拟前端（AFE）激励多个感应式触摸传感器中选定的一个感应式触摸传感器，测量多个感应触摸传感器的线圈两端的电压，并提供代表这些线圈电压的模拟输出信号。感应传感器的物理位移（触摸）导致感应式触摸传感器的电感值随着感应式触摸传感器线圈两端电压的相应变化而变化。数字处理器控制多个感应式触摸传感器中的每一个的选择，并从感应触摸AFE接收相应的模拟输出电压信号。当由数字处理器确定线圈电压的充分变化时，假定该感应式触摸传感器已被致动，并且数字处理器基于多个感应式触摸传感器中的哪一个被触发（触摸）而采取行动。

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