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1. 发明授权

US07868679B2 Circuit, method for receiving a signal, and use of a random event generator 有权
标题翻译：电路，接收信号的方法，以及随机事件发生器的使用
公开(公告)号：US07868679B2
公开(公告)日：2011-01-11
申请号：US12481249
申请日：2009-06-09
申请人： Thorsten Riedel , Jeannette Zarbock , Tilo Ferchland
发明人： Thorsten Riedel , Jeannette Zarbock , Tilo Ferchland
IPC分类号： H03H11/26
CPC分类号： H03K3/84
摘要： A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.
摘要翻译：提供一种电路，其包括用于时钟信号的输入端，用于输出随机信号，特别是随机数的随机事件发生器，连接到时钟信号的输入并连接到随机事件发生器的可设置延迟器件用于通过随机信号设置时钟信号（clk）的边沿的延迟。

2. 发明申请

US20090302920A1 CIRCUIT, METHOD FOR RECEIVING A SIGNAL, AND USE OF A RANDOM EVENT GENERATOR 有权
标题翻译：电路，接收信号的方法和随机事件发生器的使用
公开(公告)号：US20090302920A1
公开(公告)日：2009-12-10
申请号：US12481249
申请日：2009-06-09
申请人： Thorsten RIEDEL , Jeannette Zarbock , Tilo Ferchland
发明人： Thorsten RIEDEL , Jeannette Zarbock , Tilo Ferchland
IPC分类号： G06F1/04
CPC分类号： H03K3/84
摘要： A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.
摘要翻译：提供了一种电路，其包括用于时钟信号的输入端，用于输出随机信号，特别是随机数的随机事件发生器，连接到时钟信号的输入并连接到随机事件发生器的可设置延迟装置用于通过随机信号设置时钟信号（clk）的边沿的延迟。

3. 发明授权

US08193792B2 Circuit and method for operating a circuit 有权
标题翻译：用于操作电路的电路和方法
公开(公告)号：US08193792B2
公开(公告)日：2012-06-05
申请号：US12481330
申请日：2009-06-09
申请人： Wolfram Kluge , Jeannette Zarbock , Tilo Ferchland
发明人： Wolfram Kluge , Jeannette Zarbock , Tilo Ferchland
IPC分类号： G05F1/44
CPC分类号： G11C5/14 , G11C5/143 , G11C5/147
摘要： A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.
摘要翻译：提供了一种用于操作电路的电路和方法，其包括具有多个存储元件的电路部分，可以连接或连接到电路部分以便操作电路部分的第一电压调节器，第二电压调节器可以连接或连接到电路部分，以便保存存储在存储元件中的信息项，连接到电路部分并被设计为停用和激活电路部分的输入的开关装置。电路被配置为控制第一电压调节器的去激活和激活以及电路部分的输入的去激活和激活。

4. 发明申请

US20090302821A1 CIRCUIT AND METHOD FOR OPERATING A CIRCUIT 有权
标题翻译：电路运行方法
公开(公告)号：US20090302821A1
公开(公告)日：2009-12-10
申请号：US12481330
申请日：2009-06-09
申请人： Wolfram KLUGE , Jeannette Zarbock , Tilo Ferchland
发明人： Wolfram KLUGE , Jeannette Zarbock , Tilo Ferchland
IPC分类号： G05F3/02
CPC分类号： G11C5/14 , G11C5/143 , G11C5/147
摘要： A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.
摘要翻译：提供了一种用于操作电路的电路和方法，其包括具有多个存储元件的电路部分，可以连接或连接到电路部分以便操作电路部分的第一电压调节器，第二电压调节器可以连接或连接到电路部分，以便保存存储在存储元件中的信息项，连接到电路部分并被设计为停用和激活电路部分的输入的开关装置。电路被配置为控制第一电压调节器的去激活和激活以及电路部分的输入的去激活和激活。

5. 发明申请

US20120236674A1 Circuit and Method for Operating a Circuit 有权
标题翻译：电路和操作电路的方法
公开(公告)号：US20120236674A1
公开(公告)日：2012-09-20
申请号：US13485426
申请日：2012-05-31
申请人： Wolfram Kluge , Jeannette Zarbock , Tilo Ferchland
发明人： Wolfram Kluge , Jeannette Zarbock , Tilo Ferchland
IPC分类号： G11C5/14 , G05F1/10
CPC分类号： G11C5/14 , G11C5/143 , G11C5/147
摘要： A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.
摘要翻译：提供了一种用于操作电路的电路和方法，其包括具有多个存储元件的电路部分，可以连接或连接到电路部分以便操作电路部分的第一电压调节器，第二电压调节器可以连接或连接到电路部分，以便保存存储在存储元件中的信息项，连接到电路部分并被设计为停用和激活电路部分的输入的开关装置。电路被配置为控制第一电压调节器的去激活和激活以及电路部分的输入的去激活和激活。

6. 发明授权

US08030963B2 Integrated circuit and standard cell for an integrated circuit 有权
标题翻译：用于集成电路的集成电路和标准单元
公开(公告)号：US08030963B2
公开(公告)日：2011-10-04
申请号：US12817709
申请日：2010-06-17
申请人： Tilo Ferchland , Thorsten Riedel , Matthias Vorwerk
发明人： Tilo Ferchland , Thorsten Riedel , Matthias Vorwerk
IPC分类号： G06F7/50 , H03K19/21 , H03K19/20
CPC分类号： H03K19/21
摘要： In one embodiment, a cell of an integrated circuit includes a master-slave flip-flop and comparator logic having inputs adapted to receive an input signal of the master-slave flip-flop, an inverted input signal of the master-slave flip-flop, an output signal of the master-slave flip-flop, and an inverted output signal of the master-slave flip-flop. The master-slave flip-flop comprises a master flip-flop and a slave flip-flop. The slave flip-flop includes a first inverting element and a second inverting element. An output of the first inverting element is connectable to an input of the second inverting element and an output of the second inverting element to an input of the first inverting element. To output the output signal and the inverted output signal of the master-slave flip-flop, the output and the input of the second inverting element are connectable to the inputs of the comparator logic.
摘要翻译：在一个实施例中，集成电路的单元包括主从触发器和比较器逻辑，其具有适于接收主从触发器的输入信号的输入，主从触发器的反相输入信号，主从触发器的输出信号和主从触发器的反相输出信号。主从触发器包括主触发器和从触发器。从触发器包括第一反相元件和第二反相元件。第一反相元件的输出可连接到第二反相元件的输入端和第二反相元件的输出端到第一反相元件的输入端。为了输出主从触发器的输出信号和反相输出信号，第二反相元件的输出和输入可连接到比较器逻辑的输入。

7. 发明申请

US20140315508A1 Receiver and Method for the Reception of a Node by a Receiver in a Wireless Network 有权
标题翻译：用于在无线网络中由接收机接收节点的接收机和方法
公开(公告)号：US20140315508A1
公开(公告)日：2014-10-23
申请号：US14257473
申请日：2014-04-21
申请人： Tilo Ferchland , Rolf Jaehne , Frank Poegel , Eric Sachse
发明人： Tilo Ferchland , Rolf Jaehne , Frank Poegel , Eric Sachse
IPC分类号： H04B17/00 , H04W4/00 , H04W24/00
CPC分类号： H04B17/318 , H04B1/7073 , H04L7/042 , H04W4/80 , H04W24/00
摘要： In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.
摘要翻译：在一个实施例中，一种方法包括接收射频（RF）信号; 将接收到的RF信号与前导码同步以确定时基; 通过在第一时间段内平均所接收的RF信号的接收信号强度指示（RSSI）值来确定所接收的RF信号的第一能量值; 在第二时间段内确定所接收的RF信号的第二能量值; 确定所述第一能量值和所述第二能量值之间的差值; 将所述差值与预定能量阈值进行比较; 确定所接收的RF信号的质量值; 将所接收的RF信号的质量值与预定质量阈值进行比较; 并且如果差值超过预定能量阈值或质量值低于预定质量阈值，则擦除时基。

8. 发明授权

US08831553B2 Receiver and method for operating a receiver 有权
标题翻译：用于操作接收机的接收器和方法
公开(公告)号：US08831553B2
公开(公告)日：2014-09-09
申请号：US12648987
申请日：2009-12-29
申请人： Tilo Ferchland , Eric Sachse , Rolf Jaehne
发明人： Tilo Ferchland , Eric Sachse , Rolf Jaehne
IPC分类号： H04B1/16 , H04W52/02
CPC分类号： H04W52/0229 , Y02D70/144
摘要： A receiver and method for operating a receiver, in particular of a radio network, is provided, whereby the receiver includes circuit blocks in a receive path for detecting a preamble of a received signal, and a controller for controlling a receive mode. Whereby at least some of the circuit blocks are designed to be capable of being turned on for a turn-on duration and turned off for a turn-off duration. Whereby, the controller is configured to alternately turn on at least some of the circuit blocks for the turn-on duration and off for the turn-off duration during the receive mode, wherein the turn-off duration is shorter than the preamble. Whereby, the controller is configured to compare a first measured value measured in the receive path to a first threshold, and the controller is configured to change the turn-on duration and/or the turn-off duration on the basis of a result of the comparison with the first threshold, and whereby the controller is configured to compare a second measured value to a second threshold in order to detect a valid signal of the preamble and, on the basis of a result of the comparison with the second threshold, to terminate the turn-off and to drive the portion of the circuit blocks into a turned-on state for a synchronization by means of the preamble.
摘要翻译：提供了用于操作特别是无线电网络的接收机的接收机和方法，由此接收机包括用于检测接收到的信号的前同步码的接收路径中的电路块和用于控制接收模式的控制器。由此至少一些电路块被设计成能够被接通以接通持续时间，并且关断持续时间。由此，控制器被配置为在接收模式期间交替地接通导通持续时间中的至少一些电路块并且关闭关断持续时间，其中关断持续时间短于前导码。由此，控制器被配置为将在接收路径中测量的第一测量值与第一阈值进行比较，并且所述控制器被配置为基于所述接收路径的结果来改变所述接通持续时间和/或所述关断持续时间与第一阈值进行比较，由此控制器被配置为将第二测量值与第二阈值进行比较，以便检测前导码的有效信号，并且基于与第二阈值的比较结果，终止关断并且通过前置码将电路块的一部分驱动成用于同步的导通状态。

9. 发明授权

US08705670B2 Receiver and method for the reception of a node by a receiver in a wireless network 有权
标题翻译：用于由无线网络中的接收机接收节点的接收机和方法
公开(公告)号：US08705670B2
公开(公告)日：2014-04-22
申请号：US13182286
申请日：2011-07-13
申请人： Tilo Ferchland , Rolf Jaehne , Frank Poegel , Eric Sachse
发明人： Tilo Ferchland , Rolf Jaehne , Frank Poegel , Eric Sachse
IPC分类号： H04L27/06
CPC分类号： H04B17/318 , H04B1/7073 , H04L7/042 , H04W4/80 , H04W24/00
摘要： In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.
摘要翻译：在一个实施例中，一种方法包括接收射频（RF）信号; 将接收到的RF信号与前导码同步以确定时基; 通过在第一时间段内平均所接收的RF信号的接收信号强度指示（RSSI）值来确定所接收的RF信号的第一能量值; 在第二时间段内确定所接收的RF信号的第二能量值; 确定所述第一能量值和所述第二能量值之间的差值; 将所述差值与预定能量阈值进行比较; 确定所接收的RF信号的质量值; 将所接收的RF信号的质量值与预定质量阈值进行比较; 并且如果差值超过预定能量阈值或质量值低于预定质量阈值，则擦除时基。

10. 发明申请

US20140105206A1 Circuit and Method for Operating a Node in a Radio Network 有权
标题翻译：用于操作无线网络中的节点的电路和方法
公开(公告)号：US20140105206A1
公开(公告)日：2014-04-17
申请号：US14137387
申请日：2013-12-20
申请人： Tilo Ferchland , Soeren Schneider , Udo Walter
发明人： Tilo Ferchland , Soeren Schneider , Udo Walter
IPC分类号： H04W56/00 , H04L12/741
CPC分类号： H04W56/001 , H04L45/74 , H04W52/0206 , H04W88/025 , Y02D70/142 , Y02D70/144 , Y02D70/146
摘要： A circuit and a method for operating a node in a radio network, whereby nodes of the same radio network have a common network ID and each node individually is assigned a node ID, wherein during the reception of a current packet by a receiving circuit of the node, an address contained in the packet is determined, wherein reception of the current packet is continued when the determined address agrees with the network ID of the node and the node ID of the node, and wherein during reception of the current packet, the reception of the current packet is terminated and the receiving circuit is controlled based on a case decision, when the determined address does not agree with the network ID of the node or the node ID of the node.
摘要翻译：一种用于操作无线电网络中的节点的电路和方法，由此相同无线电网络的节点具有公共网络ID，并且每个节点分别被分配有节点ID，其中在由接收电路接收当前分组的过程中，确定分组中包含的地址，其中当确定的地址与节点的网络ID和节点的节点ID一致时，继续接收当前分组，并且其中在接收当前分组期间，接收当确定的地址与节点的网络ID或节点的节点ID不一致时，当前分组被终止，并且接收电路是基于情况决定来控制的。

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