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    • 1. 发明授权
    • Continuously interleaved error correction
    • 连续交错纠错
    • US08276047B2
    • 2012-09-25
    • US12270774
    • 2008-11-13
    • Tim Coe
    • Tim Coe
    • H03M13/00
    • H03M13/2792H03M13/15H03M13/152H03M13/2721H03M13/2732H03M13/2757H03M13/29H03M13/3746H03M13/6561H04L1/0041
    • Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
    • 在通信系统中使用连续交织的码字来提供纠错能力。 通常,当码字以一个顺序排列时,每个码字与先前码和后续码字共享符号,使得任何一个码字中的码元校正也校正另一个码字中的码元,并且在任何码字中校正码元可允许考虑可能 中间码字的校正,用于按码字的顺序进一步校正任何码字。 在一个实施例中,接收的信息可以被布置在子帧中,其中每个子帧包括多个码字的终端符号,多个码字中的每一个包括多个子帧中的符号。
    • 4. 发明申请
    • ADAPTIVE DATA RECOVERY SYSTEM WITH INPUT SIGNAL EQUALIZATION
    • 具有输入信号均衡的自适应数据恢复系统
    • US20090274206A1
    • 2009-11-05
    • US12366544
    • 2009-02-05
    • Tim CoeGreg Warwar
    • Tim CoeGreg Warwar
    • H03H7/30
    • H04L25/03038H04L2025/03477H04L2025/03611
    • Data receivers often include equalizers for operating on received signals. The equalizers often have a plurality of taps, with signals from each tap weighted based on tap settings or values. The tap settings may be set based on bit error rates of data output from the equalizer. In some embodiments data output from the equalizer is split into two signals, and the two signals are processed to indicate a data eye of the data output from the equalizer. Preferred tap settings may be determined by setting tap settings to different values and using tap settings expected to maximize the data eye. This may be performed separately for different bit settings in an attempt to reduce effects of inter-signal interference.
    • 数据接收器通常包括用于对接收信号进行操作的均衡器。 均衡器通常具有多个抽头,每个抽头的信号基于抽头设置或值加权。 抽头设置可以基于从均衡器输出的数据的误码率来设置。 在一些实施例中,从均衡器输出的数据被分成两个信号,并且处理这两个信号以指示从均衡器输出的数据的数据眼睛。 可以通过将tap设置设置为不同的值并使用预期的tap设置来最大化数据眼睛来确定优选的tap设置。 为了减少信号间干扰的影响,可以针对不同的位设置分别执行这一点。
    • 5. 发明授权
    • Continuously interleaved error correction
    • 连续交错纠错
    • US08887021B2
    • 2014-11-11
    • US13618380
    • 2012-09-14
    • Tim Coe
    • Tim Coe
    • H03M13/00G06F9/44H03M13/27H03M13/29H03M13/15
    • H03M13/2792H03M13/15H03M13/152H03M13/2721H03M13/2732H03M13/2757H03M13/29H03M13/3746H03M13/6561H04L1/0041
    • Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
    • 在通信系统中使用连续交织的码字来提供纠错能力。 通常,当码字以一个顺序排列时,每个码字与先前码和后续码字共享符号,使得任何一个码字中的码元校正也校正另一个码字中的码元,并且在任何码字中校正码元可允许考虑可能 中间码字的校正,用于按码字的顺序进一步校正任何码字。 在一个实施例中,接收的信息可以被布置在子帧中,其中每个子帧包括多个码字的终端符号,多个码字中的每一个包括多个子帧中的符号。
    • 6. 发明授权
    • Adaptive data recovery system with input signal equalization
    • 具有输入信号均衡的自适应数据恢复系统
    • US08705603B2
    • 2014-04-22
    • US12366544
    • 2009-02-05
    • Tim CoeGreg Warwar
    • Tim CoeGreg Warwar
    • H03H7/40
    • H04L25/03038H04L2025/03477H04L2025/03611
    • Data receivers often include equalizers for operating on received signals. The equalizers often have a plurality of taps, with signals from each tap weighted based on tap settings or values. The tap settings may be set based on bit error rates of data output from the equalizer. In some embodiments data output from the equalizer is split into two signals, and the two signals are processed to indicate a data eye of the data output from the equalizer. Preferred tap settings may be determined by setting tap settings to different values and using tap settings expected to maximize the data eye. This may be performed separately for different bit settings in an attempt to reduce effects of inter-signal interference.
    • 数据接收器通常包括用于对接收信号进行操作的均衡器。 均衡器通常具有多个抽头,每个抽头的信号基于抽头设置或值加权。 抽头设置可以基于从均衡器输出的数据的误码率来设置。 在一些实施例中,从均衡器输出的数据被分成两个信号,并且处理这两个信号以指示从均衡器输出的数据的数据眼睛。 可以通过将tap设置设置为不同的值并使用预期的tap设置来最大化数据眼睛来确定优选的tap设置。 为了减少信号间干扰的影响,可以针对不同的位设置分别执行这一点。
    • 8. 发明授权
    • Clock recovery unit which uses a detected frequency difference signal to help establish phase lock between a transmitted data signal and a recovered clock signal
    • 时钟恢复单元,其使用检测到的频差信号来帮助建立发送的数据信号和恢复的时钟信号之间的锁相
    • US06738922B1
    • 2004-05-18
    • US09680679
    • 2000-10-06
    • Greg WarwarTim Coe
    • Greg WarwarTim Coe
    • G06F104
    • H04L7/033H03L7/07H03L7/081H03L7/087H03L7/14H04L7/0083H04L7/0337
    • A clock recovery unit is used to recover a clock signal from a transmitted data signal. The clock recovery unit includes a phase locked loop (PLL) circuit and a frequency detection circuit. The frequency detection circuit includes a digital phase tracking circuit (DPTC), which uses a rotational phase shifter to shift phase of a variable clock signal from a voltage controlled oscillator in the PLL circuit, in discrete amounts from 0 to 360 degrees, depending on a digital input code provided by a digital accumulator, which receives up or down count signals from a phase comparator. The shifted variable clock signal is provided to a phase/frequency detector, which provides an output to a glitch suppressor to suppress small phase differences prior to providing the output to the PLL circuit. When the frequency difference between the variable clock signal and the reference clock signal is large, the phase/frequency detector drives the frequency in the correct direction. When the frequency difference is small, the DPTC keeps the phase of the shifted variable clock signal aligned to the phase of the reference clock signal.
    • 时钟恢复单元用于从发送的数据信号中恢复时钟信号。 时钟恢复单元包括锁相环(PLL)电路和频率检测电路。 频率检测电路包括一个数字相位跟踪电路(DPTC),该数字相位跟踪电路(DPTC)使用一个旋转移相器,从0到360度的离散量将从PLL电路中的压控振荡器的可变时钟信号的相位移位,取决于 由数字累加器提供的数字输入代码,其从相位比较器接收上行或下行计数信号。 移位的可变时钟信号被提供给相位/频率检测器,该相位/频率检测器在向PLL电路提供输出之前向毛刺抑制器提供输出以抑制小的相位差。 当可变时钟信号和参考时钟信号之间的频率差大时,相位/频率检测器以正确的方向驱动频率。 当频率差小时,DPTC保持移位的可变时钟信号的相位与参考时钟信号的相位对齐。