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1. 发明申请

US20180331817A1 LOSS OF SIGNAL DETECTION ON CDR 审中-公开
公开(公告)号：US20180331817A1
公开(公告)日：2018-11-15
申请号：US16028229
申请日：2018-07-05
申请人： INPHI CORPORATION
发明人： Parmanand MISHRA , Simon FOREY
IPC分类号： H04L7/033 , H03L7/00 , H04L12/26 , H04L27/01 , H04L25/02 , H04B17/318 , H04L7/00 , H03M9/00
CPC分类号： H04L7/0331 , H03L7/00 , H03M9/00 , H04B17/318 , H04L7/0083 , H04L7/0091 , H04L7/033 , H04L25/0262 , H04L27/01 , H04L43/04 , H04L43/16
摘要： The present invention is directed to data communication. More specifically, an embodiment of the present invention provides a technique for detecting loss of signal. An incoming data stream is sampled and a recovered clock signal is generated accordingly. An output clock signal of a higher frequency than the recovered clock signal is generated by a transmission PLL. The frequency of the recovered clock signal is compared to a divided frequency of the output clock signal. If a difference between the recovered clock signal and the output clock signal is greater than a threshold, a loss of signal indication is provided. There are other embodiments as well.

2. 发明授权

US09882703B1 Resolving meta-stability in a clock and data recovery circuit 有权
公开(公告)号：US09882703B1
公开(公告)日：2018-01-30
申请号：US15346434
申请日：2016-11-08
申请人： Xilinx, Inc.
发明人： Yu Xu , Winson Lin , Caleb S. Leung , Alan C. Wong , Christopher J. Borrelli , Yohan Frans , Kun-Yung Chang
IPC分类号： H03D3/24 , H04L7/00 , H04L12/26 , H04L7/033
CPC分类号： H04L43/16 , H04L7/0025 , H04L7/0083 , H04L7/033 , H04L25/03 , H04L43/028
摘要： An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

3. 发明授权

US09869547B2 Position-measuring device and method for testing a clock signal 有权
公开(公告)号：US09869547B2
公开(公告)日：2018-01-16
申请号：US14492115
申请日：2014-09-22
申请人： Dr. Johannes Heidenhain GmbH
发明人： Bernhard Beaury , Alexander Kobler , Stephan Kreuzer , Markus Mooshammer , Peter Spindler , Michael Walter
IPC分类号： G01R31/00 , G01R31/14 , G01C17/00 , G01B21/00 , G01D18/00 , G01R31/317 , G01D5/244 , G01D21/00 , G06F13/42 , G01D3/08 , H04L7/04 , H04L7/00
CPC分类号： G01B21/00 , G01D3/08 , G01D5/244 , G01D5/24457 , G01D18/00 , G01D21/00 , G01R31/31727 , G06F13/4295 , H04L7/0083 , H04L7/04
摘要： A position-measuring device includes a position-sensing unit, a processing unit, an interface unit, a clock generator and a time measurement unit position-sensing unit configured to generate digital position values. The processing unit processes instructions from subsequent electronics. The interface unit communicates with the subsequent electronics, according to rules of an interface protocol, via at least one interface line that transmits interface signals having a temporal behavior that is determined by the interface protocol so as to transmit the instructions from the subsequent electronics to the processing unit. The clock generator generates a clock signal that serves as a time base for functions of the position-sensing unit and the processing unit. The time measurement unit uses the clock signal as a time base, receives at least one interface signal and measures a time interval between a start event and a stop event of the at least one interface signal.

4. 发明申请

US20170373823A1 Fast Clock and Data Recovery for Free-Space Optical Communications 审中-公开
公开(公告)号：US20170373823A1
公开(公告)日：2017-12-28
申请号：US15649078
申请日：2017-07-13
申请人： Google Inc.
发明人： Leon Zhou , Sheng-Hui Yang
IPC分类号： H04L7/00 , H04B10/11 , H04L7/033
CPC分类号： H04L7/0075 , H04B10/11 , H04L7/0016 , H04L7/0029 , H04L7/0083 , H04L7/033 , H04L7/0331 , H04L7/10
摘要： A method includes receiving an optical signal through an optical link and determining a receiving power for the optical link. The method further includes comparing the receiving power for the optical link to a first receiving power threshold and transitioning a clock and data recovery circuit form a normal mode to a holdover mode when the receiving power is less than the first receiving power threshold. The clock and data recovery circuit, when operating in the holdover mode, configured to hold a recovered clock to a known-good clock frequency. When the receiving power for the optical link is greater than a second receiving power threshold, the method initiates a transition of the clock and data recovery circuit from the holdover mode to the normal mode and reacquires synchronization between the recovered clock and a current rate of the incoming data stream using the known-good clock frequency.

5. 发明申请

US20170279593A1 OPTOELECTRONIC TRANSCEIVER WITH POWER MANAGEMENT 审中-公开
公开(公告)号：US20170279593A1
公开(公告)日：2017-09-28
申请号：US15081784
申请日：2016-03-25
申请人： Intel Corporation
发明人： Rohit Mittal , David S. Dunning
IPC分类号： H04L7/00 , H04B10/40 , H04B10/516 , H04B10/564 , H04B10/69 , H04B10/50
CPC分类号： H04B10/40 , H04B10/503 , H04B10/516 , H04B10/564 , H04B10/691 , H04L7/0083
摘要： Embodiments herein relate to optoelectronic transceivers with power management. An optoelectronic device may include a photodetector, a loss of signal (LOS) detector coupled with the photodetector, and a re-timer coupled with the LOS detector, wherein a component of the re-timer is to be disabled in response to a detection by the LOS detector that an optical signal has not been received for a predetermined time period. In some embodiments, the LOS detector is coupled with a driver disable input of the re-timer and a driver component of the re-timer is to be disabled. In some embodiments, a clock data recovery circuit, a transmit module re-timer and modulator, and/or a laser may be disabled. In various embodiments, components may be re-enabled in response to detection that an optical signal is being received and/or an electrical signal is received for optical transmission. Other embodiments may be described and/or claimed.

6. 发明授权

US09621333B2 Adaptation to 3-phase signal swap within a trio 有权
公开(公告)号：US09621333B2
公开(公告)日：2017-04-11
申请号：US15270853
申请日：2016-09-20
申请人： QUALCOMM Incorporated
发明人： George Alan Wiley , Ohjoon Kwon
IPC分类号： H04L7/00 , H04L27/20 , H04L27/227 , H04L27/00 , H04B1/40
CPC分类号： H04L7/0087 , H04B1/40 , H04L7/0083 , H04L25/14 , H04L25/4923 , H04L27/0002 , H04L27/20 , H04L27/227
摘要： Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

7. 发明授权

US09537617B2 Receiver clock test circuitry and related methods and apparatuses 有权
标题翻译：接收机时钟测试电路及相关方法和装置
公开(公告)号：US09537617B2
公开(公告)日：2017-01-03
申请号：US15019483
申请日：2016-02-09
申请人： Rambus Inc.
发明人： Srinivasaraman Chandrasekaran , Kunal Desai
IPC分类号： H04B1/00 , H04L1/20 , H04L7/00 , H04L7/10 , G01R31/317 , H04L1/24
CPC分类号： H04L1/205 , G01R31/31709 , G01R31/31726 , H04L1/241 , H04L1/242 , H04L7/0079 , H04L7/0083 , H04L7/10
摘要： An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.
摘要翻译：集成电路包括多个接收器，每个接收器具有时钟和数据恢复电路。可以使第一接收机中的第一本地时钟恢复电路产生模拟要测试的条件的测试时钟，并且使包括第二本地时钟恢复电路在内的多个接收机中的第二接收机使用该测试时钟代替参考时钟，同时在其输入端接收测试数据序列。接收机中的时钟和数据恢复电路可以包括响应于环路控制信号的时钟控制环路，以响应于（i）用于正常操作或在测试期间的相应数据信号中的选择性的一个来选择性地修改所选择的参考时钟以产生本地时钟，以及（ii）施加到时钟控制回路的测试信号，在这种情况下产生测试时钟。

8. 发明授权

US09480037B2 Synchronization system and method for achieving low power battery operation of a vehicle locating unit in a stolen vehicle recovery system which receives periodic transmissions 有权
公开(公告)号：US09480037B2
公开(公告)日：2016-10-25
申请号：US14827992
申请日：2015-08-17
申请人： LoJack Corporation
发明人： Fabio Meacci , Michael Goodwin , James A. Justice , Jesse L. Rhodes
IPC分类号： H04W56/00 , H04W52/02 , H04L7/00 , H04L7/04
CPC分类号： H04W56/005 , H04L7/0079 , H04L7/0083 , H04L7/04 , H04W52/0216 , H04W52/0251 , H04W52/028 , Y02D70/00
摘要： Synchronization for achieving low power battery operation of a vehicle locating unit in a stolen vehicle recovery system whose radio receiver receives periodic transmissions, includes receiving periodic transmissions; turning on a radio receiver for a limited time to detect an expected message; if an expected message is not found, turning off the receiver and turning it on again after a time asynchronous with the transmission period; and after finding an expected message, waiting for the period of the transmissions less the length of an expected message and then looking for a synchronization symbol in the expected message and synchronizing subsequent actuation of the receiver using that synchronization symbol.

9. 发明申请

US20160294542A1 RECEPTION APPARATUS 审中-公开
标题翻译：接收装置
公开(公告)号：US20160294542A1
公开(公告)日：2016-10-06
申请号：US14910115
申请日：2015-03-16
申请人： THINE ELECTRONICS, INC.
发明人： Satoshi MIURA
IPC分类号： H04L7/033 , H04L7/04 , H03L7/091 , H04L7/00 , H03L7/08 , H03L7/099
CPC分类号： H04L7/0331 , H03L7/0807 , H03L7/091 , H03L7/099 , H04L7/0054 , H04L7/0083 , H04L7/0087 , H04L7/033 , H04L7/048 , H04L7/10
摘要： Provided is a reception apparatus capable of shortening a time period until the original data and clock can be recovered from a digital signal after temporary superimposition of noise on the digital signal stops. A reception apparatus 20 includes a receiver unit 21, a voltage-controlled oscillator 22, a sampler unit 23, a control voltage generation unit 24, an error detection unit 25, a training control unit 26, and an equalizer control unit 27. The receiver unit 21 includes an equalizer unit 21A. When the error detection unit 25 detects an error of a digital signal, the reception apparatus 20 causes a phase/frequency comparison by the control voltage generation unit 24 to be stopped.
摘要翻译：提供一种能够缩短在数字信号上暂时叠加噪声之后可以从数字信号恢复原始数据和时钟的时间段停止的接收装置。接收装置20包括接收单元21，压控振荡器22，采样单元23，控制电压生成单元24，误差检测单元25，训练控制单元26和均衡器控制单元27.接收器单元21包括均衡器单元21A。当错误检测单元25检测到数字信号的错误时，接收装置20使控制电压生成单元24进行相位/频率比较停止。

10. 发明申请

US20160293096A1 INTERNAL CLOCK SIGNAL CONTROL FOR DISPLAY DEVICE, DISPLAY DRIVER AND DISPLAY DEVICE SYSTEM 有权
标题翻译：用于显示装置，显示驱动器和显示装置系统的内部时钟信号控制
公开(公告)号：US20160293096A1
公开(公告)日：2016-10-06
申请号：US15078217
申请日：2016-03-23
申请人： Synaptics Display Devices GK
发明人： Keiji NOSE
IPC分类号： G09G3/20
CPC分类号： G09G3/2096 , G06F3/038 , G09G3/2092 , G09G5/008 , G09G2330/021 , G09G2370/08 , G09G2370/10 , H04L7/0012 , H04L7/0083 , H04N21/4305
摘要： A display device includes a display panel and a display driver driving the display panel. The display driver is connected to a host with a clock lane and at least one a data lane. The display driver includes: an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal; a control circuit configured to output an internal clock signal synchronous with the external clock signal; and a drive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal fed from the control circuit. The control circuit is configured to feed the internal clock signal in response to a type of a reception packet included in the reception data.
摘要翻译：显示装置包括显示面板和驱动显示面板的显示驱动器。显示驱动器连接到具有时钟通道和至少一个数据通道的主机。显示驱动器包括：接口电路，被配置为经由时钟通道从主机接收外部时钟信号，经由数据通道从主机接收数据信号，并输出通过数据信号发送的接收数据; 控制电路，被配置为输出与所述外部时钟信号同步的内部时钟信号; 以及驱动电路，被配置为与从控制电路馈送的内部时钟信号同步地响应于包含在接收数据中的图像数据来驱动显示面板。控制电路被配置为响应于包含在接收数据中的接收分组的类型来馈送内部时钟信号。

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