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1. 发明申请

US20080209382A1 STITCHED IC CHIP LAYOUT DESIGN STRUCTURE 失效
标题翻译： STITCHED IC芯片布局设计结构
公开(公告)号：US20080209382A1
公开(公告)日：2008-08-28
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译：公开了拼接集成电路（IC）芯片布局设计结构。在一个实施例中，体现在设计过程中使用的机器可读介质中的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片，所述IC芯片布局包括：至少包括多个缝合区域一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。

2. 发明授权

US07707535B2 Stitched IC chip layout design structure 失效
标题翻译：拼接IC芯片布局设计结构
公开(公告)号：US07707535B2
公开(公告)日：2010-04-27
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip layout exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译：公开了拼接集成电路（IC）芯片布局设计结构。在一个实施例中，在设计过程中使用的机器可读介质中体现的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片布局，所述IC芯片布局包括：多个缝合区域，至少一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。

3. 发明申请

US20080208383A1 STITCHED IC CHIP LAYOUT METHODS, SYSTEMS AND PROGRAM PRODUCT 失效
标题翻译： STITCHED IC芯片布局方法，系统和程序产品
公开(公告)号：US20080208383A1
公开(公告)日：2008-08-28
申请号：US11678069
申请日：2007-02-23
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F19/00
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.
摘要翻译：公布了拼接集成电路（IC）芯片布局方法，系统和程序产品。在一个实施例中，一种方法包括从第一实体获得超过第二实体上的光刻工具区域的尺寸的IC芯片布局的电路设计，其中IC芯片布局包括用于多个缝合区域：识别发生缝合的至少一个缝合区域的边界的边界标识和指示所述至少一个缝合区域是否是以下之一的类型指示器：冗余且唯一; 将IC芯片布局解剖为在第二实体处表示为唯一或冗余的缝合区域; 以及基于所述多个缝合区域在所述第二实体处产生光刻掩模版，所述光刻掩模版具有适合在所述第二实体处的所述光刻工具区域的尺寸内的尺寸。

4. 发明授权

US07703060B2 Stitched IC layout methods, systems and program product 失效
标题翻译：拼接IC布局方法，系统和程序产品
公开(公告)号：US07703060B2
公开(公告)日：2010-04-20
申请号：US11678069
申请日：2007-02-23
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.
摘要翻译：公布了拼接集成电路（IC）芯片布局方法，系统和程序产品。在一个实施例中，一种方法包括从第一实体获得超过第二实体上的光刻工具区域的尺寸的IC芯片布局的电路设计，其中IC芯片布局包括用于多个缝合区域：识别发生缝合的至少一个缝合区域的边界的边界标识和指示所述至少一个缝合区域是否是以下之一的类型指示器：冗余且唯一; 将IC芯片布局解剖为在第二实体处表示为唯一或冗余的缝合区域; 以及基于所述多个缝合区域在所述第二实体处产生光刻掩模版，所述光刻掩模版具有适合在所述第二实体处的所述光刻工具区域的尺寸内的尺寸。

5. 发明申请

US20090276748A1 STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT 有权
标题翻译：针对IC芯片布局布线的电路区域边界标注
公开(公告)号：US20090276748A1
公开(公告)日：2009-11-05
申请号：US12112329
申请日：2008-04-30
申请人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
发明人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
IPC分类号： G06F17/50
CPC分类号： G03F7/70475
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译：针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

6. 发明授权

US08006211B2 IC chip and design structure including stitched circuitry region boundary identification 有权
标题翻译： IC芯片和设计结构包括缝合电路区域边界识别
公开(公告)号：US08006211B2
公开(公告)日：2011-08-23
申请号：US12112336
申请日：2008-04-30
申请人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
发明人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译：针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

7. 发明授权

US07958482B2 Stitched circuitry region boundary identification for stitched IC chip layout 有权
标题翻译：缝合IC芯片布局的缝合电路区域边界识别
公开(公告)号：US07958482B2
公开(公告)日：2011-06-07
申请号：US12112329
申请日：2008-04-30
申请人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
发明人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
IPC分类号： G06F17/50
CPC分类号： G03F7/70475
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译：针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

8. 发明申请

US20090276739A1 IC CHIP AND DESIGN STRUCTURE INCLUDING STITCHED CIRCUITRY REGION BOUNDARY IDENTIFICATION 有权
标题翻译： IC芯片和设计结构，包括纹路电路区域边界识别
公开(公告)号：US20090276739A1
公开(公告)日：2009-11-05
申请号：US12112336
申请日：2008-04-30
申请人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
发明人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译：针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

9. 发明授权

US08753917B2 Method of fabricating photoconductor-on-active pixel device 有权
标题翻译：制造感光体活性像素装置的方法
公开(公告)号：US08753917B2
公开(公告)日：2014-06-17
申请号：US12967625
申请日：2010-12-14
申请人： Jeffrey P. Gambino , Robert K. Leidy , Richard J. Rassel
发明人： Jeffrey P. Gambino , Robert K. Leidy , Richard J. Rassel
IPC分类号： H01L31/112
CPC分类号： H01L31/105 , H01L27/14632 , H01L27/14636 , H01L27/14665 , H01L27/14687
摘要： A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括设置在中间层上的第一介电层，设置在第一介电层上的第一导电焊盘部分和第一互连部分，设置在第一介电层上的第二介电层电介质层，设置在第一互连部分上的第一覆盖层和第一导电焊盘部分的一部分，设置在第一覆盖层上的第二封盖层和第二介电层的一部分，设置n型掺杂硅层在第二覆盖层和第一导电焊盘部分上，设置在n型掺杂硅层上的本征硅层和设置在本征硅层上的p型掺杂硅层。

10. 发明申请

US20090302406A1 DELAMINATION AND CRACK RESISTANT IMAGE SENSOR STRUCTURES AND METHODS 有权
标题翻译：分层和抗裂图像传感器结构与方法
公开(公告)号：US20090302406A1
公开(公告)日：2009-12-10
申请号：US12132875
申请日：2008-06-04
申请人： Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Charles F. Musante , Richard J. Rassel
发明人： Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Charles F. Musante , Richard J. Rassel
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L27/14627 , H01L27/1463 , H01L27/14632 , H01L27/14636
摘要： A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.
摘要翻译：多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供了相对于多个图像传感器结构内的平坦化层的透镜封盖层的抑制性破裂和分层。特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分之上的有源透镜层不同的至少一个虚拟透镜层。另外特定的图像传感器结构包括平坦化层内的孔径和位于特定图像传感器结构内的电路部分上方的平坦化层的倾斜端壁中的至少一个。

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