专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20170263443A1 TRENCH AND HOLE PATTERNING WITH EUV RESISTS USING DUAL FREQUENCY CAPACITIVELY COUPLED PLASMA (CCP) 审中-公开
公开(公告)号：US20170263443A1
公开(公告)日：2017-09-14
申请号：US15458476
申请日：2017-03-14
申请人： Tokyo Electron Limited
发明人： Hiroie Matsumoto , Andrew W. Metz , Yannick Feurprier , Katie Lutker-Lee
IPC分类号： H01L21/027 , G03F7/20 , H01L21/311
CPC分类号： H01L21/0274 , G03F7/20 , G03F7/2004 , H01L21/0273 , H01L21/31058 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.

2. 发明授权

US10332744B2 Method for patterning a substrate using a layer with multiple materials 有权
公开(公告)号：US10332744B2
公开(公告)日：2019-06-25
申请号：US15581708
申请日：2017-04-28
申请人： Tokyo Electron Limited
发明人： Anton J. deVilliers , Andrew W. Metz
IPC分类号： H01L21/033 , H01L21/311 , H01L21/3205 , H01L21/3105 , H01L21/321
摘要： Techniques herein include forming single or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. A relatively thin portion of mandrel material stretches from a base of mandrels to each other and underneath sidewall spacers and other fill materials, thereby forming a film of mandrel material over an underlying layer, which provides advantages with etch selectivity in a patterning process. Accordingly a multi-line layer is formed with materials having different etch resistivities to be able to selectively etch one or more of the materials to create features where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer.

3. 发明授权

US11121027B2 High aspect ratio via etch using atomic layer deposition protection layer 有权
公开(公告)号：US11121027B2
公开(公告)日：2021-09-14
申请号：US16213628
申请日：2018-12-07
申请人： Tokyo Electron Limited
发明人： Yen-Tien Lu , Xinghua Sun , Eric Chih-Fang Liu , Andrew W. Metz
IPC分类号： H01L21/768 , H01L21/311 , H01L21/02
摘要： A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.

4. 发明申请

US20190181041A1 High Aspect Ratio Via Etch Using Atomic Layer Deposition Protection Layer 审中-公开
公开(公告)号：US20190181041A1
公开(公告)日：2019-06-13
申请号：US16213628
申请日：2018-12-07
申请人： Tokyo Electron Limited
发明人： Yen-Tien Lu , Xinghua Sun , Eric Chih-Fang Liu , Andrew W. Metz
IPC分类号： H01L21/768 , H01L21/311 , H01L21/02
摘要： A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.

5. 发明申请

US20170316939A1 Method for Patterning a Substrate Using a Layer with Multiple Materials 审中-公开
公开(公告)号：US20170316939A1
公开(公告)日：2017-11-02
申请号：US15581708
申请日：2017-04-28
申请人： Tokyo Electron Limited
发明人： Anton J. deVilliers , Andrew W. Metz
IPC分类号： H01L21/033 , H01L21/3105
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/31053 , H01L21/311 , H01L21/3205 , H01L21/321
摘要： Techniques herein include forming single or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. A relatively thin portion of mandrel material stretches from a base of mandrels to each other and underneath sidewall spacers and other fill materials, thereby forming a film of mandrel material over an underlying layer, which provides advantages with etch selectivity in a patterning process. Accordingly a multi-line layer is formed with materials having different etch resistivities to be able to selectively etch one or more of the materials to create features where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer.

6. 发明授权

US09818610B2 Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP) 有权
公开(公告)号：US09818610B2
公开(公告)日：2017-11-14
申请号：US15458476
申请日：2017-03-14
申请人： Tokyo Electron Limited
发明人： Hiroie Matsumoto , Andrew W. Metz , Yannick Feurprier , Katie Lutker-Lee
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , H01L21/027 , H01L21/311 , G03F7/20
CPC分类号： H01L21/0274 , G03F7/20 , G03F7/2004 , H01L21/0273 , H01L21/31058 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.

7. 发明授权

US09607834B2 Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP) 有权
公开(公告)号：US09607834B2
公开(公告)日：2017-03-28
申请号：US15088701
申请日：2016-04-01
申请人： Tokyo Electron Limited
发明人： Hiroie Matsumoto , Andrew W. Metz , Yannick Feurprier , Katie Lutker-Lee
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , H01L21/027 , G03F7/20 , H01L21/311 , H01L21/3105
CPC分类号： H01L21/0274 , G03F7/20 , G03F7/2004 , H01L21/0273 , H01L21/31058 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer. The method further includes repeating the selective depositing and etching, at least until the complete thickness of the non-masked portions of the antireflective coating layer is removed, to expose the underlying organic layer.

8. 发明申请

US20160293405A1 TRENCH AND HOLE PATTERNING WITH EUV RESISTS USING DUAL FREQUENCY CAPACITIVELY COUPLED PLASMA (CCP) 有权
标题翻译：使用双频电容耦合等离子体（CCP）对EUV电阻进行TRENCH和HOLE
公开(公告)号：US20160293405A1
公开(公告)日：2016-10-06
申请号：US15088701
申请日：2016-04-01
申请人： Tokyo Electron Limited
发明人： Hiroie Matsumoto , Andrew W. Metz , Yannick Feurprier , Katie Lutker-Lee
IPC分类号： H01L21/027 , G03F7/20 , H01L21/311
CPC分类号： H01L21/0274 , G03F7/20 , G03F7/2004 , H01L21/0273 , H01L21/31058 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer. The method further includes repeating the selective depositing and etching, at least until the complete thickness of the non-masked portions of the antireflective coating layer is removed, to expose the underlying organic layer.
摘要翻译：公开了一种在衬底上蚀刻抗反射涂层的方法。基板包括有机层，设置在有机层上方的抗反射涂层以及设置在抗反射涂层之上的光致抗蚀剂层。该方法包括图案化光致抗蚀剂层以暴露抗反射涂层的非掩蔽部分，并且在抗反射涂层的非掩蔽部分和图案化光致抗蚀剂层的非侧壁部分上选择性地沉积含碳层。该方法还包括蚀刻薄膜叠层以除去含碳层并除去抗反射涂层的非掩蔽部分的部分厚度，而不会减小光致抗蚀剂层的厚度。该方法还包括重复选择性沉积和蚀刻，至少直到除去抗反射涂层的非掩蔽部分的完整厚度以露出下面的有机层。

9. 发明授权

US09396958B2 Self-aligned patterning using directed self-assembly of block copolymers 有权
标题翻译：使用嵌段共聚物的定向自组装的自对准图案
公开(公告)号：US09396958B2
公开(公告)日：2016-07-19
申请号：US14865128
申请日：2015-09-25
申请人： Tokyo Electron Limited
发明人： Andrew W. Metz , Anton J. deVilliers
IPC分类号： H01L21/30 , H01L21/308
CPC分类号： H01L21/3086 , H01L21/0271 , H01L21/3081 , H01L21/3088 , H01L21/31133 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： Techniques herein provide methods for self-aligned etching that use existing features for patterning or registering a pattern, without damaging existing features. Existing substrate structures are used to create a surface that enables directed self-assembly (DSA) of block copolymers (BCP) without a separate lithographic patterning layer. Methods herein include recessing at least one existing material or structure on a substrate, and adding a film that remains on the recessed material only. This film can be selected to have a preferential surface energy that enables controlled self-assembly of block copolymers. The substrate can then be etched using both existing structures and one polymer material as an etching mask. One example advantage is that self-assembled polymer material can be located to protect exposed corners of existing features, which reduces a burden of selective etch chemistry, increases precision of subsequent etching, and reduces sputter yield.
摘要翻译：本文中的技术提供了使用现有特征进行图案化或注册图案的自对准蚀刻的方法，而不损害现有特征。使用现有的基底结构来产生表面，其使得无需单独的平版印刷图案层的嵌段共聚物（BCP）的定向自组装（DSA）。本文的方法包括在衬底上凹陷至少一个现有材料或结构，并且仅添加仅保留在凹陷材料上的膜。可以选择该膜具有能够控制嵌段共聚物自组装的优先表面能。然后可以使用现有结构和一种聚合物材料作为蚀刻掩模蚀刻该衬底。一个示例性的优点是可以定位自组装的聚合物材料以保护现有特征的暴露角，这减少了选择性蚀刻化学的负担，提高随后蚀刻的精度，并降低溅射产率。

10. 发明授权

US10854453B2 Method for reducing reactive ion etch lag in low K dielectric etching 有权
公开(公告)号：US10854453B2
公开(公告)日：2020-12-01
申请号：US16005614
申请日：2018-06-11
申请人： Tokyo Electron Limited
发明人： Angelique D. Raley , Christopher Cole , Andrew W. Metz
IPC分类号： H01L21/033 , H01L21/311 , H01L21/02
摘要： A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式