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1. 发明申请

US20090015292A1 Semiconductor device having transfer gate between pre-buffer and main buffer 有权
标题翻译：具有预缓冲器和主缓冲器之间的传输门的半导体器件
公开(公告)号：US20090015292A1
公开(公告)日：2009-01-15
申请号：US12213780
申请日：2008-06-24
申请人： Tomoya Nishitani , Kenichi Kawakami
发明人： Tomoya Nishitani , Kenichi Kawakami
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： A semiconductor device includes a pre-buffer for transferring a data signal on the basis of a first power supply voltage, a main buffer for amplifying and outputting the data signal transferred by the pre-buffer on the basis of a second power supply voltage different from the first power supply voltage, a switch unit for controlling a conductive state between the pre-buffer and the main buffer on the basis of a switch control signal, and a control circuit for generating the switch control signal for controlling the pre-buffer to set an output level of the pre-buffer to ground potential in accordance with transition of logical level of the switch control signal.
摘要翻译：半导体器件包括用于基于第一电源电压传送数据信号的预缓冲器，用于根据不同于第一电源电压的第二电源电压放大并输出由预缓冲器传送的数据信号的主缓冲器第一电源电压，用于基于开关控制信号控制预缓冲器和主缓冲器之间的导通状态的开关单元，以及用于产生用于控制预缓冲器设置的开关控制信号的控制电路根据开关控制信号的逻辑电平的转换，预缓冲器到地电位的输出电平。

2. 发明授权

US07663407B2 Semiconductor device having transfer gate between pre-buffer and main buffer 有权
标题翻译：具有预缓冲器和主缓冲器之间的传输门的半导体器件
公开(公告)号：US07663407B2
公开(公告)日：2010-02-16
申请号：US12213780
申请日：2008-06-24
申请人： Tomoya Nishitani , Kenichi Kawakami
发明人： Tomoya Nishitani , Kenichi Kawakami
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： A semiconductor device includes a pre-buffer for transferring a data signal on the basis of a first power supply voltage, a main buffer for amplifying and outputting the data signal transferred by the pre-buffer on the basis of a second power supply voltage different from the first power supply voltage, a switch unit for controlling a conductive state between the pre-buffer and the main buffer on the basis of a switch control signal, and a control circuit for generating the switch control signal for controlling the pre-buffer to set an output level of the pre-buffer to ground potential in accordance with transition of logical level of the switch control signal.
摘要翻译：半导体器件包括用于基于第一电源电压传送数据信号的预缓冲器，用于根据不同于第一电源电压的第二电源电压放大并输出由预缓冲器传送的数据信号的主缓冲器第一电源电压，用于基于开关控制信号控制预缓冲器和主缓冲器之间的导通状态的开关单元，以及用于产生用于控制预缓冲器设置的开关控制信号的控制电路根据开关控制信号的逻辑电平的转换，预缓冲器到地电位的输出电平。

3. 发明授权

US08384480B2 Differential amplifier 有权
标题翻译：差分放大器
公开(公告)号：US08384480B2
公开(公告)日：2013-02-26
申请号：US13244467
申请日：2011-09-24
申请人： Michimasa Yamaguchi , Kenichi Kawakami
发明人： Michimasa Yamaguchi , Kenichi Kawakami
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F2203/45318 , H03F2203/45394 , H03F2203/45396
摘要： A differential amplifier includes first and second current paths, each connected between first and second power supplies (PS) and respectively outputting first and second differential output signals. The first current path includes: first transistor, selectively interconnected between the first PS and a first output terminal, its gate receiving one differential input signal; second transistor, connected between the second PS and the first output terminal, its gate receiving the other differential input signal; and first switch circuit. The second current path includes: third transistor, selectively interconnected between the second PS and a second output terminal, its gate receiving one differential input signal; fourth transistor, connected between the first PS and the second output terminal, its gate receiving the other differential input signal; and second switch circuit. One of the first and second switch circuits is connected to the first PS and the other is connected to the second PS.
摘要翻译：差分放大器包括第一和第二电流路径，每个电流路径连接在第一和第二电源（PS）之间，并分别输出第一和第二差分输出信号。第一电流路径包括：第一晶体管，选择性地互连在第一PS和第一输出端之间，其栅极接收一个差分输入信号; 第二晶体管，连接在第二PS和第一输出端之间，其栅极接收另一个差分输入信号; 和第一开关电路。第二电流路径包括：第三晶体管，选择性地互连在第二PS和第二输出端之间，其栅极接收一个差分输入信号; 第四晶体管，连接在第一PS和第二输出端之间，其栅极接收另一个差分输入信号; 和第二开关电路。第一和第二开关电路中的一个连接到第一PS，另一个连接到第二PS。

4. 发明授权

US5969365A Charged-particle-beam exposure device and charged-particle-beam exposure method 失效
公开(公告)号：US5969365A
公开(公告)日：1999-10-19
申请号：US917464
申请日：1997-08-26
申请人： Akio Takemoto , Yoshihisa Ooaeh , Tomohiko Abe , Hiroshi Yasuda , Takamasa Satoh , Hideki Nasuno , Hidefumi Yabara , Kenichi Kawakami , Kiichi Sakamoto , Tomohiro Sakazaki , Isamu Seto , Masami Takigawa , Tatsuro Ohkawa
发明人： Akio Takemoto , Yoshihisa Ooaeh , Tomohiko Abe , Hiroshi Yasuda , Takamasa Satoh , Hideki Nasuno , Hidefumi Yabara , Kenichi Kawakami , Kiichi Sakamoto , Tomohiro Sakazaki , Isamu Seto , Masami Takigawa , Tatsuro Ohkawa
IPC分类号： G21K5/10 , H01J37/08 , H01J37/302 , H01J37/304
CPC分类号： H01J37/147 , B82Y10/00 , B82Y40/00 , H01J37/21 , H01J37/3045 , H01J37/3174 , H01J2237/024 , H01J2237/1502 , H01J2237/1504 , H01J2237/216 , H01J2237/30472
摘要： A method of exposing a wafer to a charged-particle beam by directing to the wafer the charged-particle beam deflected by a deflector includes the steps of arranging a plurality of first marks at different heights, focusing the charged-particle beam on each of the first marks by using a focus coil provided above the deflector, obtaining a focus distance for each of the first marks, obtaining deflection-efficiency-correction coefficients for each of the first marks, and using linear functions of the focus distance for approximating the deflection-efficiency-correction coefficients to obtain the deflection-efficiency-correction coefficients for an arbitrary value of the focus distance. A device for carrying out the method is also set forth.

5. 发明授权

US07492193B2 Driver circuit 失效
标题翻译：驱动电路
公开(公告)号：US07492193B2
公开(公告)日：2009-02-17
申请号：US11325302
申请日：2006-01-05
申请人： Kenichi Kawakami
发明人： Kenichi Kawakami
IPC分类号： H03K3/00
CPC分类号： H03K19/00384 , H03K19/018528
摘要： A driver circuit that prevents amplitude reduction at a high temperature comprises a differential pre-buffer circuit 22 for performing signal clamping by diodes 16 and 17 each having a nonlinear voltage-current characteristic with respect to an input signal and a differential output circuit 23 for amplifying output signals of the differential pre-buffer circuit 22, for output. The driver circuit further includes a temperature characteristic compensation circuit 44 for controlling direct currents to be passed through the diodes 16 and 17 based on a current to be passed through a diode 43 having a voltage-current characteristic with the same temperature coefficient as those of the diodes 16 and 17. A current related to constant currents I1 and I2 is supplied from the temperature characteristic compensation circuit 44 as a current that cancels the temperature characteristic of a fall in forward voltages of the diodes 16 and 17.
摘要翻译：防止高温降幅的驱动电路包括差分预缓冲器电路22，用于通过二极管16和17进行信号钳位，二极管16和17各自具有相对于输入信号的非线性电压电流特性和用于放大的差分输出电路23 输出差分预缓冲电路22的输出信号。驱动器电路还包括温度特性补偿电路44，用于基于要通过二极管43的电流控制要通过二极管16和17的直流电流，该二极管43具有与具有相同温度系数的电压 - 电流特性二极管16和17.与恒定电流I1和I2相关的电流从温度特性补偿电路44提供为消除二极管16和17的正向电压下降的温度特性的电流。

6. 发明申请

US20070127614A1 Communication device 审中-公开
标题翻译：通讯设备
公开(公告)号：US20070127614A1
公开(公告)日：2007-06-07
申请号：US11634082
申请日：2006-12-06
申请人： Kenichi Kawakami
发明人： Kenichi Kawakami
IPC分类号： H03D3/24
CPC分类号： H04L7/0091 , H03L7/06 , H04L1/243 , H04L7/0337
摘要： Disclosed is a communication circuit including a clock selection circuit (20) which receives CDR multiple-phase clocks (16) from a PLL (1) to a CDR circuit (7), selects one of the CDR multiple-phase clock signals (16) responsive to a clock selection signal (21), and outputs the selected clock signal. At a time of the loopback test, the clock signal selected by the clock selection circuit (20) is used as a transmit clock (11). Transmit data is looped back from an input/output terminal (4) to a receiver circuit (6). Data from the receiver circuit (6) is supplied to the CDR circuit (7), and comparison between recovered data from the CDR circuit (7) and expected value data is made by a comparison circuit (8), thereby conducting the test. By changing a phase of the transmit clock (11) by the clock selection circuit (20), a delay time (=tTx+tRx) which is a sum of a transmit circuit delay time (tTx) and a receiver circuit delay time (tRx) can be varied.
摘要翻译：公开了一种通信电路，包括从PLL（1）向CDR电路（7）接收CDR多相时钟（16）的时钟选择电路（20），选择CDR多相时钟信号（16）中的一个，响应于时钟选择信号（21），并输出所选择的时钟信号。在环回测试时，由时钟选择电路（20）选择的时钟信号用作发送时钟（11）。发送数据从输入/输出端子（4）回送到接收器电路（6）。来自接收器电路（6）的数据被提供给CDR电路（7），并且通过比较电路（8）进行来自CDR电路（7）的恢复数据与期望值数据的比较，从而进行测试。通过由时钟选择电路（20）改变发送时钟（11）的相位，作为发送电路延迟时间（tTx）和接收机电路延迟时间（tRx）之和的延迟时间（= tTx + tRx））可以变化。

7. 发明授权

US06420700B2 Charged-particle-beam exposure device and charged-particle-beam exposure method 有权
标题翻译：带电粒子束曝光装置和带电粒子束曝光方法
公开(公告)号：US06420700B2
公开(公告)日：2002-07-16
申请号：US09826913
申请日：2001-04-06
申请人： Yoshihisa Ooaeh , Kenichi Kawakami
发明人： Yoshihisa Ooaeh , Kenichi Kawakami
IPC分类号： H01J37304
CPC分类号： H01J37/147 , B82Y10/00 , B82Y40/00 , H01J37/21 , H01J37/3045 , H01J37/3174 , H01J2237/024 , H01J2237/1502 , H01J2237/1504 , H01J2237/216 , H01J2237/30472
摘要： A method of exposing a wafer to a charged-particle beam by directing to the wafer the charged-particle beam deflected by a deflector includes the steps of arranging a plurality of first marks at different heights, focusing the charged-particle beam on each of the first marks by using a focus coil provided above the deflector, obtaining a focus distance for each of the first marks, obtaining deflection-efficiency-correction coefficients for each of the first marks, and using linear functions of the focus distance for approximating the deflection-efficiency-correction coefficients to obtain the deflection-efficiency-correction coefficients for an arbitrary value of the focus distance. A device for carrying out the method is also set forth.
摘要翻译：通过将晶片引导到晶片，通过偏转器偏转的带电粒子束将晶片暴露于带电粒子束的方法包括以下步骤：在不同的高度处布置多个第一标记，将带电粒子束聚焦在每个通过使用设置在偏转器上方的聚焦线圈的第一标记，获得每个第一标记的聚焦距离，获得每个第一标记的偏转效率校正系数，并且使用焦距的线性函数来近似偏转 - 效率校正系数，以获得针对焦距的任意值的偏转效率校正系数。还提出了一种用于执行该方法的装置。

8. 发明授权

US6002296A Filter circuit with an intermittent constant current with constant period 失效
标题翻译：具有恒定周期的间歇恒定电流的滤波电路
公开(公告)号：US6002296A
公开(公告)日：1999-12-14
申请号：US928771
申请日：1997-09-12
申请人： Kenichi Kawakami
发明人： Kenichi Kawakami
IPC分类号： H03F3/45 , H03H11/04 , H03B1/00
CPC分类号： H03H11/04
摘要： A periodic low current from an intermittent Low current generator 5 is used, and fluctuations of r1 and r10, c1 and c2, and I6 and I20, thus cancel one another. Thus, .omega..sub.0 is not fluctuated unless the oscillation frequency Tosc of a pulse wave generator OSC is fluctuated. Television and ratio audio ICs using an LPF filter do not require specific provision of any oscillator for a filter circuit, because they have an accurate oscillator. The oscillation frequency of the pulse wave generator OSC should be at least 20 times the pass band of the filter circuit.
摘要翻译：使用来自间歇低电流发生器5的周期性低电流，并且r1和r10，c1和c2以及I6和I20的波动因此彼此抵消。因此，除非脉冲波发生器OSC的振荡频率Tosc波动，否则ω0不波动。使用LPF滤波器的电视和比例音频IC不需要为滤波器电路提供任何振荡器，因为它们具有精确的振荡器。脉冲波发生器OSC的振荡频率应至少为滤波电路通带的20倍。

9. 发明授权

US5830612A Method of detecting a deficiency in a charged-particle-beam exposure mask 失效
标题翻译：检测带电粒子束曝光掩模缺陷的方法
公开(公告)号：US5830612A
公开(公告)日：1998-11-03
申请号：US711935
申请日：1996-09-11
申请人： Akio Yamada , Satoru Sagou , Hitoshi Watanabe , Satoru Yamazaki , Kiichi Sakamoto , Manabu Ohno , Kenichi Kawakami , Katsuhiko Kobayashi
发明人： Akio Yamada , Satoru Sagou , Hitoshi Watanabe , Satoru Yamazaki , Kiichi Sakamoto , Manabu Ohno , Kenichi Kawakami , Katsuhiko Kobayashi
IPC分类号： G03F1/00 , G03F1/20 , H01J37/304 , H01J37/317 , G03F9/00 , G03C5/00
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/86 , H01J37/3045 , H01J37/3174 , G03F1/20 , H01J2237/2817 , H01J2237/31794
摘要： A method of detecting deficiency of an aperture used in a charged-particle-beam exposure process employing at least two exposure columns is disclosed, where each of the two exposure columns passes a charged-particle beam through the aperture formed through a mask to shape a cross section of the charged-particle beam before exposing the charged-particle beam onto an object. The method includes the steps of mounting masks having the same aperture to the at least two exposure columns; scanning, in each of the at least two exposure columns, the charged-particle beam over an area containing a mark on a surface substantially at the same height as the object after passing the charged-particle beam through the same aperture; obtaining, in each of the at least two exposure columns, a signal waveform corresponding to the scan by detecting charged particles scattered by the mark; and comparing the signal waveform between the at least two exposure columns.
摘要翻译：公开了一种检测在使用至少两个曝光柱的带电粒子束曝光工艺中使用的孔的缺陷的方法，其中两个曝光柱中的每一个通过带电粒子束穿过通过掩模形成的孔以形成在将带电粒子束暴露在物体上之前的带电粒子束的横截面。该方法包括以下步骤：将具有相同孔径的掩模安装到至少两个曝光柱; 在所述至少两个曝光柱中的每一个中，在将带电粒子束通过相同的孔之后，将包含在与物体基本上处于相同高度的表面上的标记的区域上的带电粒子束扫描; 在所述至少两个曝光列中的每一个中，通过检测由所述标记散射的带电粒子来获得对应于所述扫描的信号波形; 以及比较所述至少两个曝光列之间的信号波形。

10. 发明授权

US08125274B2 Differential amplifier 有权
标题翻译：差分放大器
公开(公告)号：US08125274B2
公开(公告)日：2012-02-28
申请号：US12801304
申请日：2010-06-02
申请人： Michimasa Yamaguchi , Kenichi Kawakami
发明人： Michimasa Yamaguchi , Kenichi Kawakami
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F2203/45318 , H03F2203/45394 , H03F2203/45396
摘要： A differential amplifier including: 1st transistor that is connected between 1st power-supply terminal and 1st output terminal, and has a control terminal receiving one of the differential input signals; 2nd transistor that is connected between 2nd power-supply terminal and 1st output terminal, and has a control terminal receiving the other of the differential input signals; 1st switch that is connected between 1st power-supply terminal and 1st transistor; 3rd transistor that is connected between 2nd power-supply terminal and 2nd output terminal, and has a control terminal receiving one of the differential input signals; 4th transistor that is connected between 1st power-supply terminal and 2nd output terminal, and has a control terminal receiving the other of the differential input signals; 2nd switch that is connected between 2nd power-supply terminal and 3rd transistor. Drive state of 1st and 2nd switches are controlled by a control signal.
摘要翻译：一种差分放大器，包括：连接在第一电源端子和第一输出端子之间的第一晶体管，并具有接收差分输入信号之一的控制端子; 第二晶体管连接在第二电源端子和第一输出端子之间，并具有接收另一个差分输入信号的控制端子; 连接在第一电源端子和第一晶体管之间的第一开关; 第三晶体管连接在第二电源端子和第二输出端子之间，并具有接收差分输入信号之一的控制端子; 第四晶体管，连接在第一电源端子和第二输出端子之间，并具有接收另一个差分输入信号的控制端子; 连接在第二电源端子和第三晶体管之间的第二开关。第一和第二开关的驱动状态由控制信号控制。

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