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1. 发明申请

US20100097150A1 PLL CIRCUIT 审中-公开
标题翻译： PLL电路
公开(公告)号：US20100097150A1
公开(公告)日：2010-04-22
申请号：US12252443
申请日：2008-10-16
申请人： Keisuke Ueda , Toshiya Uozumi , Satoru Yamamoto , Mitsunori Samata , Russell P. Mohn , Aleksander Dec , Ken Suyama
发明人： Keisuke Ueda , Toshiya Uozumi , Satoru Yamamoto , Mitsunori Samata , Russell P. Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/08
CPC分类号： H03L7/1976 , H03L7/089 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal.
摘要翻译：提供一种用于抑制由于在PLL电路中对模拟电路进行数字化而产生的量化噪声的技术。 PLL电路包括：数字相位频率检测器，其检测（比较）参考信号的相位和频率以及分频信号，并将其转换为数字值; 数字环路滤波器，其从数字相位频率比较器的输出消除高频噪声分量; 数字模拟转换器，其将数字环路滤波器的输出的数字值转换为模拟值; 模拟滤波器，其从数字 - 模拟转换器的输出消除高频噪声分量; 基于模拟滤波器的输出来控制频率的压控振荡器; 以及分频器，其分压电压控制振荡器的频率并输出分频信号。

2. 发明授权

US08754713B2 PLL circuit with improved phase difference detection 有权
标题翻译： PLL电路具有改进的相位差检测
公开(公告)号：US08754713B2
公开(公告)日：2014-06-17
申请号：US12952705
申请日：2010-11-23
申请人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , H03K5/135 , H03L7/093 , H03L7/193
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译：在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。反馈回路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。

3. 发明授权

US07859344B2 PLL circuit with improved phase difference detection 有权
标题翻译： PLL电路具有改进的相位差检测
公开(公告)号：US07859344B2
公开(公告)日：2010-12-28
申请号：US12111458
申请日：2008-04-29
申请人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , H03K5/135 , H03L7/093 , H03L7/193
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译：在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。反馈环路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。

4. 发明申请

US20090267664A1 PLL CIRCUIT 有权
标题翻译： PLL电路
公开(公告)号：US20090267664A1
公开(公告)日：2009-10-29
申请号：US12111458
申请日：2008-04-29
申请人： Toshiya UOZUMI , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P. Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya UOZUMI , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P. Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/06
CPC分类号： H03L7/091 , H03K5/135 , H03L7/093 , H03L7/193
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译：在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。反馈环路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。

5. 发明申请

US20070188203A1 Semiconductor integrated circuit having built-in PLL circuit 有权
公开(公告)号：US20070188203A1
公开(公告)日：2007-08-16
申请号：US11730236
申请日：2007-03-30
申请人： Yasuyuki Kimura , Satoshi Shimizu , Masakatsu Yokota , Ken Suyama , Aleksander Dec
发明人： Yasuyuki Kimura , Satoshi Shimizu , Masakatsu Yokota , Ken Suyama , Aleksander Dec
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/0898 , H03L7/107 , H03L7/1072 , H03L7/1075
摘要： A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

6. 发明授权

US07015735B2 Semiconductor integrated circuit having built-in PLL circuit 有权
标题翻译：具有内置PLL电路的半导体集成电路
公开(公告)号：US07015735B2
公开(公告)日：2006-03-21
申请号：US10739117
申请日：2003-12-19
申请人： Yasuyuki Kimura , Satoshi Shimizu , Masakatsu Yokota , Ken Suyama , Aleksander Dec
发明人： Yasuyuki Kimura , Satoshi Shimizu , Masakatsu Yokota , Ken Suyama , Aleksander Dec
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/0898 , H03L7/107 , H03L7/1072 , H03L7/1075
摘要： A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.
摘要翻译：一种具有内置PLL电路的半导体集成电路，其具有响应于由相位比较器电路产生的信号而具有用于对环路滤波器的电容元件进行充电和放电的两个电荷泵电路。两个电荷泵电路中的一个具有产生比另一个电荷泵电路的电流源产生的电流值小的电流源的电流源。环路滤波器具有连接到充电/放电节点的第一电容元件和通过电阻元件连接到充电/放电节点的第二电容元件。第一电容元件由一个电荷泵电路充电和放电，而第二电容元件被另一个电荷泵电路充电和放电。一个电荷泵电路的充电电流源与另一个电荷泵电路的放电电流源同时操作，即电荷泵电路以相反的相位工作。

7. 发明授权

US07336138B2 Embedded structure circuit for VCO and regulator 有权
标题翻译： VCO和调节器的嵌入式结构电路
公开(公告)号：US07336138B2
公开(公告)日：2008-02-26
申请号：US11412973
申请日：2006-04-28
申请人： Tomomitsu Kitamura , Ken Suyama , Aleksander Dec
发明人： Tomomitsu Kitamura , Ken Suyama , Aleksander Dec
IPC分类号： H03B5/12 , H03L1/00
CPC分类号： H03L7/099 , H03B5/04 , H03B5/1215 , H03B5/1228 , H03B5/1231 , H03B5/1243 , H03B2200/0062 , H03L5/00 , H03L7/0891 , H03L7/18
摘要： An oscillation circuit formed in a single semiconductor chip, wherein a first source voltage is supplied to a first power supply terminal, a second source voltage different from the first source voltage is supplied to a second power supply terminal, a voltage regulator receives the voltage from the first power supply terminal and outputs a source voltage, a voltage controlled oscillation circuit is supplied with a source voltage from the voltage regulator, a current source circuit is connected to the second power supply terminal, the voltage regulator, the voltage controlled oscillation circuit and the current source circuit are inserted in series between the first and second power supply terminals, and the current supplied to the voltage controlled oscillation circuit from the voltage regulator flows in the current source circuit.
摘要翻译：一种形成在单个半导体芯片中的振荡电路，其中第一电源电压被提供给第一电源端子，与第一电源电压不同的第二源极电压被提供给第二电源端子，电压调节器接收来自第一电源端子输出源电压，电压控制振荡电路从电压调节器提供源电压，电流源电路连接到第二电源端子，电压调节器，压控振荡电路和电流源电路串联插在第一和第二电源端子之间，并且从电压调节器提供给压控振荡电路的电流在电流源电路中流动。

8. 发明授权

US06906596B2 Oscillation circuit and a communication semiconductor integrated circuit 失效
标题翻译：振荡电路和通信半导体集成电路
公开(公告)号：US06906596B2
公开(公告)日：2005-06-14
申请号：US10253922
申请日：2002-09-25
申请人： Tomomitsu Kitamura , Yasuyuki Kimura , Ken Suyama , Aleksander Dec
发明人： Tomomitsu Kitamura , Yasuyuki Kimura , Ken Suyama , Aleksander Dec
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04 , H03B5/12 , H03L5/00 , H03L7/099 , H03L7/10 , H03L7/00
CPC分类号： H03L7/10 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1253 , H03B5/1262 , H03B5/1293 , H03L5/00 , H03L7/099
摘要： A voltage controlled LC resonance oscillation circuit has a plurality of capacitive elements connected to an output node. These capacitive elements are applied with voltages at opposing terminals for selecting an oscillating frequency band, so that the oscillating frequency band can be changed step by step in accordance with the selection voltage. The capacitive elements include at least one variable capacitive element such as a MOS capacitor, the capacitance of which is varied in accordance with a voltage applied thereto. The MOS capacitor is similar in structure to a MOS transistor. The variable capacitive element can be supplied at a terminal opposite to the output node with a voltage from a variable voltage source, for example, in place of the selection voltage. The voltage controlled LC resonance oscillation circuit can measure the output amplitude and oscillating frequency without affecting the characteristics thereof, and reduce the parasitic capacitance.
摘要翻译：电压控制LC谐振振荡电路具有连接到输出节点的多个电容元件。这些电容元件在相对端子处施加电压以选择振荡频带，使得可以根据选择电压逐步改变振荡频带。电容元件包括至少一个可变电容元件，例如MOS电容器，其电容根据施加到其上的电压而变化。 MOS电容器的结构类似于MOS晶体管。可变电容元件可以在与输出节点相对的端子处具有来自可变电压源的电压，例如代替选择电压。电压LC共振振荡电路可以测量输出幅度和振荡频率，而不影响其特性，并降低寄生电容。

9. 发明授权

US07689191B2 Semiconductor integrated circuit having built-in PLL circuit 有权
标题翻译：具有内置PLL电路的半导体集成电路
公开(公告)号：US07689191B2
公开(公告)日：2010-03-30
申请号：US11730236
申请日：2007-03-30
申请人： Yasuyuki Kimura , Satoshi Shimizu , Masakatsu Yokota , Ken Suyama , Aleksander Dec
发明人： Yasuyuki Kimura , Satoshi Shimizu , Masakatsu Yokota , Ken Suyama , Aleksander Dec
IPC分类号： H04B7/00
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/0898 , H03L7/107 , H03L7/1072 , H03L7/1075
摘要： A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.
摘要翻译：一种具有内置PLL电路的半导体集成电路，其具有响应于由相位比较器电路产生的信号而具有用于对环路滤波器的电容元件进行充电和放电的两个电荷泵电路。两个电荷泵电路中的一个具有产生比另一个电荷泵电路的电流源产生的电流值小的电流源的电流源。环路滤波器具有连接到充电/放电节点的第一电容元件和通过电阻元件连接到充电/放电节点的第二电容元件。第一电容元件由一个电荷泵电路充电和放电，而第二电容元件被另一个电荷泵电路充电和放电。一个电荷泵电路的充电电流源与另一个电荷泵电路的放电电流源同时操作，即电荷泵电路以相反的相位工作。

10. 发明申请

US20070273415A1 Semiconductor integrated circuit having built-in PLL circuit 审中-公开
标题翻译：具有内置PLL电路的半导体集成电路
公开(公告)号：US20070273415A1
公开(公告)日：2007-11-29
申请号：US11730819
申请日：2007-04-04
申请人： Yasuyuki Kimura , Satoshi Shimizu , Masakatsu Yokota , Ken Suyama , Aleksander Dec
发明人： Yasuyuki Kimura , Satoshi Shimizu , Masakatsu Yokota , Ken Suyama , Aleksander Dec
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/0898 , H03L7/107 , H03L7/1072 , H03L7/1075
摘要： A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.
摘要翻译：一种具有内置PLL电路的半导体集成电路，其具有响应于由相位比较器电路产生的信号而具有用于对环路滤波器的电容元件进行充电和放电的两个电荷泵电路。两个电荷泵电路中的一个具有产生比另一个电荷泵电路的电流源产生的电流值小的电流源的电流源。环路滤波器具有连接到充电/放电节点的第一电容元件和通过电阻元件连接到充电/放电节点的第二电容元件。第一电容元件由一个电荷泵电路充电和放电，而第二电容元件由另一个电荷泵电路充电和放电。一个电荷泵电路的充电电流源与另一个电荷泵电路的放电电流源同时操作，即电荷泵电路以相反的相位工作。

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