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1. 发明公开

US20230412176A1 METHOD AND SYSTEM OF DYNAMICALLY CONTROLLING RESET SIGNAL OF IQ DIVIDER 审中-公开
公开(公告)号：US20230412176A1
公开(公告)日：2023-12-21
申请号：US17947845
申请日：2022-09-19
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Praveen RATHEE , Vishnu KALYANAMAHADEVI GOPALAN JAWARLAL , Sanjeeb Kumar GHOSH , Avneesh Singh VERMA
IPC分类号： H03L7/193 , H03K21/08 , H03K5/135 , H03L7/14
CPC分类号： H03L7/193 , H03K21/08 , H03K5/135 , H03L7/148
摘要： A system and method to dynamically control a reset signal for an IQ divider are provided. The system includes an IQ divider configured to output a IQ divider output clock; an input configured to receive a reference clock; a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit including an automatic frequency calibration (AFC) logic; and a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.

2. 发明公开

US20230194694A1 OSCILLATOR CIRCUIT, CORRESPONDING RADAR SENSOR, VEHICLE AND METHOD OF OPERATION 审中-公开
公开(公告)号：US20230194694A1
公开(公告)日：2023-06-22
申请号：US18108993
申请日：2023-02-13
申请人： STMicroelectronics S.r.l.
发明人： Alessandro PARISI , Andrea CAVARRA , Alessandro FINOCCHIARO , Giuseppe PAPOTTO , Giuseppe PALMISANO
IPC分类号： G01S13/58 , G01S7/40 , G01S13/931 , H03B5/12 , H03L7/193 , H03L7/099 , H03L7/10
CPC分类号： G01S13/584 , G01S7/4056 , G01S13/931 , H03B5/1212 , H03B5/1228 , H03L7/193 , H03B5/1265 , H03B5/1293 , H03L7/099 , H03L7/101 , H03L7/103 , H03B5/1243
摘要： Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.

3. 发明申请

US20190036533A1 VARIABLE FREQUENCY DIVIDER 审中-公开
公开(公告)号：US20190036533A1
公开(公告)日：2019-01-31
申请号：US16071978
申请日：2016-03-16
申请人： Mitsubishi Electric Corporation
发明人： Yuki YANAGIHARA , Koji TSUTSUMI
IPC分类号： H03K21/08
CPC分类号： H03K21/08 , H03K23/64 , H03K23/667 , H03L7/18 , H03L7/193
摘要： A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

4. 发明申请

US20170264425A1 HIGH ORDER HYBRID PHASE LOCKED LOOP WITH DIGITAL SCHEME FOR JITTER SUPPRESSION 有权
公开(公告)号：US20170264425A1
公开(公告)日：2017-09-14
申请号：US15064975
申请日：2016-03-09
申请人： Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi
发明人： Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi
IPC分类号： H04L7/033
CPC分类号： H04L7/0331 , H03L7/06 , H03L7/07 , H03L7/0802 , H03L7/0805 , H03L7/081 , H03L7/0814 , H03L7/085 , H03L7/087 , H03L7/093 , H03L7/099 , H03L7/0992 , H03L7/18 , H03L7/1806 , H03L7/193 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/06 , H03L2207/50
摘要： A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

5. 发明申请

US20170099059A1 APPARATUS AND METHODS FOR TUNING A VOLTAGE CONTROLLED OSCILLATOR 审中-公开
公开(公告)号：US20170099059A1
公开(公告)日：2017-04-06
申请号：US15287570
申请日：2016-10-06
申请人： Skyworks Solutions, Inc.
发明人： Hua Wang , David Steven Ripley , Brian J. Roll
IPC分类号： H03L7/099 , H03L7/193 , H03L7/187
CPC分类号： H03L7/0992 , H03B1/00 , H03B5/1265 , H03B5/1271 , H03L1/00 , H03L7/099 , H03L7/10 , H03L7/18 , H03L7/187 , H03L7/193
摘要： Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

6. 发明授权

US09444465B1 Low phase noise frequency divider 有权
标题翻译：低相位噪声分频器
公开(公告)号：US09444465B1
公开(公告)日：2016-09-13
申请号：US14666060
申请日：2015-03-23
申请人： Peregrine Semiconductor Corporation
发明人： Gary Chunshien Wu
IPC分类号： H03L7/06 , H03K23/42 , H03L7/08
CPC分类号： H03K23/42 , H03L7/193 , H03L7/1976
摘要： A low phase noise frequency divider suitable for use in phase locked loops (PLL) and frequency synthesizers, particular in a fractional-N PLL system having an N frequency divider with a main (M) counter and an auxiliary (A) counter. In some user selectable cases, the count value CM for the M counter is fixed and only the count value CA for the A counter is varied. Having a fixed CM value results in lower phase noise in most cases. For cases where it is not possible to vary CM, then CM is allowed to vary in a conventional manner to retain a full range of functionality.
摘要翻译：适用于锁相环（PLL）和频率合成器的低相位噪声分频器，特别是在具有N（M）计数器和辅助（A）计数器的N分频器的分数N PLL系统中。在一些用户选择的情况下，M计数器的计数值CM是固定的，并且仅A计数器的计数值CA是变化的。在大多数情况下，具有固定的CM值可导致较低的相位噪声。对于不可能改变CM的情况，允许CM以常规方式变化以保持全部功能。

7. 发明申请

US20160164527A1 DIGITAL PHASE-LOCKED LOOP AND METHOD OF OPERATING THE SAME 有权
标题翻译：数字锁相环及其操作方法
公开(公告)号：US20160164527A1
公开(公告)日：2016-06-09
申请号：US14955802
申请日：2015-12-01
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Min-young SONG , Tae-ik KIM , Ji-hyun KIM
IPC分类号： H03L7/081 , H03L7/095 , H03L7/08 , H03L7/099
CPC分类号： H03L7/0814 , H03L7/0802 , H03L7/081 , H03L7/087 , H03L7/095 , H03L7/099 , H03L7/0992 , H03L7/193 , H03L2207/06
摘要： Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.
摘要翻译：提供了具有改进的信号特性的数字锁相环（DPLL）以及操作DPLL的方法。 DPLL包括：第一跟踪单元，被配置为接收参考信号和通过反馈DPLL的输出信号，跟踪反馈信号并输出延迟的参考信号而产生的反馈信号;以及第二跟踪单元，被配置为接收通过延迟反馈信号产生的延迟反馈信号和延迟的参考信号，并产生DPLL的输出信号，其根据延迟的反馈信号和延迟的参考信号之间的相位差来控制频率。

8. 发明授权

US09197276B2 Semiconductor device, radio communication terminal, and method for controlling semiconductor device 有权
标题翻译：半导体装置，无线通信终端以及半导体装置的控制方法
公开(公告)号：US09197276B2
公开(公告)日：2015-11-24
申请号：US14083629
申请日：2013-11-19
申请人： Renesas Mobile Corporation
发明人： Ryo Endo
IPC分类号： H04B7/00 , H04B1/40 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/193
CPC分类号： H04L7/033 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/193 , H03L2207/50 , H04B1/1036 , H04B1/40
摘要： A semiconductor device according to the present invention includes a PLL circuit, in which the PLL circuit includes: a phase difference detection unit that detects a phase difference between a reference signal and a division signal; a filter that outputs a control signal according to a detection result of the phase difference detection unit; an oscillation unit that outputs an oscillation signal of a frequency according to the control signal; a division unit that divides the oscillation signal to output it as the division signal; a noise intensity detection unit that detects a noise intensity of a predetermined frequency component included in the control signal; and a phase difference adjustment unit that adjusts a phase difference between the reference signal and the division signal based on the noise intensity detected by the noise intensity detection unit.
摘要翻译：根据本发明的半导体器件包括PLL电路，其中PLL电路包括：相位差检测单元，其检测参考信号和除法信号之间的相位差; 滤波器，其根据所述相位差检测单元的检测结果输出控制信号; 振荡单元，其根据所述控制信号输出频率的振荡信号; 分割单元，其将振荡信号分频，将其输出作为除法信号; 噪声强度检测单元，其检测包括在所述控制信号中的预定频率分量的噪声强度; 以及相位差调整单元，其基于由噪声强度检测单元检测到的噪声强度来调整基准信号与除法信号之间的相位差。

9. 发明申请

US20150236847A1 SIGNAL-GENERATING CIRCUIT AND WIRELESS COMMUNICATION DEVICE 有权
标题翻译：信号发生电路和无线通信设备
公开(公告)号：US20150236847A1
公开(公告)日：2015-08-20
申请号：US14610271
申请日：2015-01-30
申请人： Panasonic Corporation
发明人： KOJI TAKINAMI , TAKAYUKI TSUKIZAWA , KENJI MIYANAGA , SHUNSUKE HIRANO
IPC分类号： H04L7/033 , H04B1/00 , H04B1/405
CPC分类号： H03L7/16 , H03L7/18 , H03L7/193 , H04B1/403 , H04B1/408
摘要： A signal-generating circuit includes a voltage-controlled oscillator that generates an oscillated signal; a first frequency divider that generates a first divided signal by dividing the oscillated signal; a second frequency divider that generates a second divided signal by dividing the divided signal; a phase comparator that receives as input the second divided signal and a reference signal and outputs two signals corresponding to a phase difference therebetween; a loop filter that extracts a low frequency signal between the two signals to be output to the voltage-controlled oscillator; a third frequency divider that generates a third divided signal by dividing the first divided signal; a first frequency converter that generates a first frequency converted signal by multiplying the oscillated signal by the third divided signal; and a first multiplier that generates a multiplied signal by multiplying the first frequency converted signal by a first multiplication number.
摘要翻译：信号发生电路包括产生振荡信号的压控振荡器; 第一分频器，通过分频振荡信号产生第一分频信号; 第二分频器，通过划分分频信号产生第二分频信号; 相位比较器，接收第二分频信号和参考信号作为输入，并输出对应于它们之间的相位差的两个信号; 环路滤波器，提取要输出到压控振荡器的两个信号之间的低频信号; 第三分频器，通过划分第一分频信号产生第三分频信号; 第一频率转换器，其通过将所述振荡信号乘以所述第三分频信号来产生第一频率转换信号; 以及第一乘法器，通过将第一频率转换信号乘以第一乘法数来产生相乘的信号。

10. 发明授权

US09042854B2 Apparatus and methods for tuning a voltage controlled oscillator 有权
标题翻译：用于调谐压控振荡器的装置和方法
公开(公告)号：US09042854B2
公开(公告)日：2015-05-26
申请号：US14101094
申请日：2013-12-09
申请人： SKYWORKS SOLUTIONS, INC.
发明人： Hua Wang , David Steven Ripley , Bryan J. Roll
IPC分类号： H04B1/16 , H03L7/18 , H03L7/099 , H03L7/10 , H03L7/187 , H03L7/193
CPC分类号： H03L7/0992 , H03L7/099 , H03L7/10 , H03L7/18 , H03L7/187 , H03L7/193
摘要： Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
摘要翻译：提供了用于调谐压控振荡器（VCO）的装置和方法。一方面，一种在锁相环路中进行自整定的方法包括使用耦合到电容器阵列的VCO来产生VCO时钟信号，使用具有可选择划分的预分频器电路分频VCO时钟信号以产生分频时钟信号使用计数器模块的第一计数器和第二计数器来控制可选分频比的值，使用计数器模块生成基于分割控制信号M的相位频率检测器反馈信号和分频时钟信号，计数一个使用数字处理逻辑电路的周期计数器在校准间隔期间发生的划分的时钟信号的周期数，以及基于在校准间隔期间计数的周期数来确定电容器阵列控制信号的值。

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