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1. 发明申请

US20100332887A1 STORAGE CONTROL DEVICE HAVING CONTROLLER OPERATED ACCORDING TO DETECTION SIGNAL DERIVED FROM MONITORING POWER SIGNAL AND RELATED METHOD THEREOF 审中-公开
标题翻译：具有根据监视功率信号发送的检测信号操作的控制器的存储控制装置及其相关方法
公开(公告)号：US20100332887A1
公开(公告)日：2010-12-30
申请号：US12727256
申请日：2010-03-19
申请人： Tzu-Chieh Lin , Tzu-Li Hung , Kuan-Hua Chao , Shiue-Shin Liu , Hong-Ching Chen , Li-Chun Tu
发明人： Tzu-Chieh Lin , Tzu-Li Hung , Kuan-Hua Chao , Shiue-Shin Liu , Hong-Ching Chen , Li-Chun Tu
IPC分类号： G06F11/30 , G06F12/00
CPC分类号： G11C5/143 , G06F12/0246 , G06F2212/7201 , G11C16/30
摘要： One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range.
摘要翻译：用于存储介质的一个示例性存储控制装置包括控制器和电压检测器，其中控制器控制存储介质的数据访问，并且电压检测器监视电源信号，并且断言检测信号以在电源异常时通知控制器检测到信号。用于存储介质的另一示例性存储控制装置包括电压检测器和控制器，其中电压检测器监视功率信号以产生检测信号，并且控制器控制存储介质的数据访问。此外，当检测信号指示电力信号的电压水平落在第一电压范围内时，控制器进入第一操作状态，并且当检测信号指示电力信号的电压水平下降时，控制器进入第二操作状态在第二电压范围内。

2. 发明申请

US20090296869A1 COMMUNICATION SYSTEMS, CLOCK GENERATION CIRCUITS THEREOF, AND METHOD FOR GENERATING CLOCK SIGNAL 有权
标题翻译：通信系统，其产生电路及其产生时钟信号的方法
公开(公告)号：US20090296869A1
公开(公告)日：2009-12-03
申请号：US12407226
申请日：2009-03-19
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/081 , H03L7/087 , H03L7/1974
摘要： A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.
摘要翻译：提供时钟发生电路并且包括锁相环（PLL）和校准器。 PLL被布置成接收第一时钟信号并产生输出时钟信号。 PLL根据控制信号调节输出时钟信号的频率。校准器被布置成接收输出时钟信号和第二时钟信号，在输出时钟信号和第二时钟信号之间执行频率校准，并根据频率校准的结果产生控制信号。

3. 发明授权

US08526559B2 Communication systems and clock generation circuits thereof with reference source switching 有权
标题翻译：具有参考源切换的通信系统及其时钟发生电路
公开(公告)号：US08526559B2
公开(公告)日：2013-09-03
申请号：US12410502
申请日：2009-03-25
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Tse-Hsiang Hsu
IPC分类号： H03D3/24
CPC分类号： H04L7/0091 , H04B15/02 , H04B2215/067 , H04L7/0083
摘要： A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL generates the output clock signal according to a second clock signal.
摘要翻译：提供了一种用于根据输出时钟信号发送数据的发送器的时钟发生电路。时钟发生电路包括时钟发生器和锁相环（PLL）。时钟发生器产生第一个时钟信号。 PLL最初根据第一个时钟信号产生输出时钟信号。当根据第一时钟信号产生的输出时钟信号的频率不在指定发送器所需的范围内时，PLL根据第二时钟信号产生输出时钟信号。

4. 发明申请

US20090296870A1 COMMUNICATION SYSTEMS AND CLOCK GENERATION CIRCUITS THEREOF WITH REFERENCE SOURCE SWITCHING 有权
标题翻译：具有参考源切换的通信系统和时钟发生电路
公开(公告)号：US20090296870A1
公开(公告)日：2009-12-03
申请号：US12410502
申请日：2009-03-25
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Tse-Hsiang Hsu
IPC分类号： H04L7/00
CPC分类号： H04L7/0091 , H04B15/02 , H04B2215/067 , H04L7/0083
摘要： A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL switches to generate the output clock signal according to a second clock signal.
摘要翻译：提供了一种用于根据输出时钟信号发送数据的发送器的时钟发生电路。时钟发生电路包括时钟发生器和锁相环（PLL）。时钟发生器产生第一个时钟信号。 PLL最初根据第一个时钟信号产生输出时钟信号。当根据第一时钟信号产生的输出时钟信号的频率不在指定发送器所需的范围内时，PLL切换以根据第二时钟信号产生输出时钟信号。

5. 发明授权

US08451971B2 Communication systems, clock generation circuits thereof, and method for generating clock signal 有权
标题翻译：通信系统，其时钟生成电路以及用于产生时钟信号的方法
公开(公告)号：US08451971B2
公开(公告)日：2013-05-28
申请号：US12407226
申请日：2009-03-19
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/081 , H03L7/087 , H03L7/1974
摘要： A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.
摘要翻译：提供时钟发生电路并且包括锁相环（PLL）和校准器。 PLL被布置成接收第一时钟信号并产生输出时钟信号。 PLL根据控制信号调节输出时钟信号的频率。校准器被布置成接收输出时钟信号和第二时钟信号，在输出时钟信号和第二时钟信号之间执行频率校准，并根据频率校准的结果产生控制信号。

6. 发明授权

US08537937B2 Detecting circuit and related detecting method 有权
标题翻译：检测电路及相关检测方法
公开(公告)号：US08537937B2
公开(公告)日：2013-09-17
申请号：US12987146
申请日：2011-01-09
申请人： Kuan-Hua Chao , Tzu-Li Hung , Yu-Bang Nian
发明人： Kuan-Hua Chao , Tzu-Li Hung , Yu-Bang Nian
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H04B1/16 , H03K5/19
摘要： A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair.
摘要翻译：检测电路包括：第一偏移生成电路，被布置为向包括正输入信号和负输入信号的输入信号对施加第一偏移，并且因此产生包括第一正输出信号和第一负输出的第一输出信号对信号; 以及耦合到所述第一偏移生成电路的第一采样电路，所述第一采样电路被布置成对所述第一正输出信号和所述第一负输出信号之间的电压差进行采样，以产生第一采样信号，其中利用所述第一采样信号以识别输入信号对上的数据信号。

7. 发明申请

US20120177146A1 DETECTING CIRCUIT AND RELATED DETECTING METHOD 有权
标题翻译：检测电路及相关检测方法
公开(公告)号：US20120177146A1
公开(公告)日：2012-07-12
申请号：US12987146
申请日：2011-01-09
申请人： Kuan-Hua Chao , Tzu-Li Hung , Yu-Bang Nian
发明人： Kuan-Hua Chao , Tzu-Li Hung , Yu-Bang Nian
IPC分类号： H04L27/00
CPC分类号： H04B1/16 , H03K5/19
摘要： A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair.
摘要翻译：检测电路包括：第一偏移生成电路，被布置为向包括正输入信号和负输入信号的输入信号对施加第一偏移，并且因此产生包括第一正输出信号和第一负输出的第一输出信号对信号; 以及耦合到所述第一偏移生成电路的第一采样电路，所述第一采样电路被布置成对所述第一正输出信号和所述第一负输出信号之间的电压差进行采样，以产生第一采样信号，其中利用所述第一采样信号以识别输入信号对上的数据信号。

8. 发明申请

US20090278574A1 Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider 有权
标题翻译：分频器，分频方式和利用分频器的锁相环
公开(公告)号：US20090278574A1
公开(公告)日：2009-11-12
申请号：US12437541
申请日：2009-05-07
申请人： Hong-Sing Kao , Meng-Ta Yang , Kuan-Hua Chao , Tse-Hsiang Hsu
发明人： Hong-Sing Kao , Meng-Ta Yang , Kuan-Hua Chao , Tse-Hsiang Hsu
IPC分类号： H03K23/00 , H03L7/06
CPC分类号： H03L7/183 , H03K5/133 , H03K21/023 , H03K2005/00058 , H03K2005/00234
摘要： A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.
摘要翻译：分频器减少抖动和功耗，并且包括用于接收多个时钟信号并输出对应于至少一个时钟信号的相位特性的中间信号的相位选择器和用于接收中间信号的可调延迟电路，以及通过延迟所接收的中间信号来产生输出信号。

9. 发明申请

US20080253492A1 CIRCUIT AND METHOD FOR CONTROLLING MIXED MODE CONTROLLED OSCILLATOR AND CDR CIRCUIT USING THE SAME 有权
标题翻译：用于控制混合模式控制的振荡器和CDR电路的电路和方法
公开(公告)号：US20080253492A1
公开(公告)日：2008-10-16
申请号：US12060315
申请日：2008-04-01
申请人： Ping-Ying Wang , Kuan-Hua Chao , Jeng-Horng Tsai
发明人： Ping-Ying Wang , Kuan-Hua Chao , Jeng-Horng Tsai
IPC分类号： H03D3/24
CPC分类号： H03L9/00 , H03K3/0315 , H03K5/133 , H03K2005/00032 , H03K2005/00071 , H03K2005/00195 , H03K2005/00234 , H03L7/089 , H03L7/0891 , H03L7/0995 , H03L7/113 , H04L7/033
摘要： A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.
摘要翻译：一种用于控制混合模式控制振荡器的电路。电路包括电荷泵和数字环路滤波器。电荷泵耦合到混合模式受控振荡器。电荷泵接收上/下信号并将电流信号发送到混合模式受控振荡器。数字环路滤波器接收上/下信号，并向混合模式控制振荡器产生数字码信号。混合模式控制振荡器的输出频率由电流信号和数字代码信号控制。

10. 发明授权

US07936180B2 Serial link transmitter 有权
标题翻译：串行链路发射机
公开(公告)号：US07936180B2
公开(公告)日：2011-05-03
申请号：US12265774
申请日：2008-11-06
申请人： Kuan-Hua Chao , Chih-Chien Hung , Pao-Cheng Chiu
发明人： Kuan-Hua Chao , Chih-Chien Hung , Pao-Cheng Chiu
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G06F13/4072 , H04L25/0272 , H04L25/028 , Y02D10/14 , Y02D10/151
摘要： The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.
摘要翻译：本发明提供一种串行链路发射机，其通过一对传输线耦合到串行链路接收机，并具有分别耦合到传输线之一的一对发射终端。串行链路发射机包括差分放大器和钳位电路。差分放大器根据用于将数据发送到串行链路接收机的一对差分输入电压在发送端子上产生一对差分输出电压，并且在数据期间差分输出电压以共模电压发送到串行链路接收器传输。在串行链路发射机向串行链路接收机发送数据之前，钳位电路将发送端子的差分输出电压对钳到共模电压。

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