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1. 发明授权

US11126550B1 Integrating a resistive memory system into a multicore CPU die to achieve massive memory parallelism 有权
公开(公告)号：US11126550B1
公开(公告)日：2021-09-21
申请号：US16121339
申请日：2018-09-04
申请人： University of Maryland at College Park , Crossbar, Inc.
发明人： Donald Yeung , Bruce L. Jacob , Mehdi Asnaashari , Sylvain Dubois
IPC分类号： G11C11/00 , G06F12/0802 , G11C13/00 , H01L27/24
摘要： Disclosed is a monolithic integrated circuit (IC) computing device with multiple independent process cores (multicore) and embedded, non-volatile resistive memory serving as system memory. The resistive system memory is fabricated above the substrate, and logic circuits embodying the process cores are fabricated on the substrate. In addition, access circuitry for operating on the resistive system memory, and circuitry embodying memory controllers, routing devices and other logic components is provided at least in part on the substrate. Large main memory capacities of tens or hundreds of gigabytes (GB) are provided and operable with many process cores, all on a single die. This monolithic integration provides close physical proximity between the process cores and main memory, facilitating significant memory parallelism, reduced power consumption, and eliminating off-chip main memory access requests.

2. 发明授权

US11727986B2 Physically unclonable function (PUF) generation involving programming of marginal bits 有权
公开(公告)号：US11727986B2
公开(公告)日：2023-08-15
申请号：US17503890
申请日：2021-10-18
申请人： Crossbar Inc.
发明人： Mehdi Asnaashari , Sung Hyun Jo
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/004 , G11C13/0038
摘要： Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

3. 发明授权

US10699785B2 Computing memory architecture 有权
公开(公告)号：US10699785B2
公开(公告)日：2020-06-30
申请号：US16144771
申请日：2018-09-27
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari , Hagop Nazarian , Christophe Sucur , Sylvain Dubois
IPC分类号： G11C11/00 , G11C13/00 , G11C7/18 , G11C8/12 , G11C29/42 , G11C29/44 , G11C8/14 , G06F17/16 , G11C29/04
摘要： Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.

4. 发明授权

US10592429B1 Cache management for memory module comprising two-terminal resistive memory 有权
公开(公告)号：US10592429B1
公开(公告)日：2020-03-17
申请号：US15615253
申请日：2017-06-06
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari , Robin Sarno , Ruchirkumar D. Shah
IPC分类号： G06F12/08 , G06F12/1045 , G06F12/1009 , G11C11/406 , G06F12/02 , G06F12/0802 , G06F12/0815
摘要： Cache memory for resistive switching memory modules is provided herein. The cache memory can reside on a separate DIMM from the resistive switching memory, in some embodiments, or can share a common DIMM with the resistive switching memory. Cache management protocols are provided to service read and write policies for managing interaction of data between the cache memory and the resistive switching memory. In various embodiments, memory controllers are optimized for physical characteristics of resistive switching memory, and cache management protocols can be implemented to take advantage of these characteristics.

5. 发明授权

US10409714B1 Logical to physical translation for two-terminal memory 有权
公开(公告)号：US10409714B1
公开(公告)日：2019-09-10
申请号：US15428721
申请日：2017-02-09
申请人： Crossbar, Inc.
发明人： Ruchirkumar Shah , Mehdi Asnaashari
IPC分类号： G06F12/02
摘要： One potential result of differing characteristics for certain two-terminal memory (TTM) is that memory management techniques, such as logical-to-physical (L2P), can differ as well. Previous memory management techniques do not adequately leverage the advantages associated with TTM. For example, by identifying and leveraging certain advantageous characteristics of TTM, L2P tables can be designed to be smaller and more efficient, which can allow the L2P table to be stored in memory that is faster and/or closer (or integrated into) an associated controller. Moreover, other memory management operations such as wear-leveling, recovery from power loss, and so forth, can be more efficient.

6. 发明授权

US10347335B2 Node retainer circuit incorporating RRAM 有权
公开(公告)号：US10347335B2
公开(公告)日：2019-07-09
申请号：US15926394
申请日：2018-03-20
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari , Hagop Nazarian
IPC分类号： G11C13/00 , G11C14/00
摘要： A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.

7. 发明授权

US10056907B1 Field programmable gate array utilizing two-terminal non-volatile memory 有权
公开(公告)号：US10056907B1
公开(公告)日：2018-08-21
申请号：US15593371
申请日：2017-05-12
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari , Hagop Nazarian , Sang Nguyen
IPC分类号： H03K19/17 , H03K19/00 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/0013 , H03K19/17728 , H03K19/17744 , H03K19/1776 , H03K19/17776
摘要： A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.

8. 发明授权

US09916105B1 Page management for data operations utilizing a memory device 有权
公开(公告)号：US09916105B1
公开(公告)日：2018-03-13
申请号：US14933032
申请日：2015-11-05
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari
IPC分类号： G06F3/06 , G06F12/08 , G06F12/0802
CPC分类号： G06F3/0629 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F12/0802 , G06F2212/2024 , G06F2212/601 , G11C7/1012 , G11C7/1063 , G11C7/1075 , G11C7/20 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： Providing for a memory apparatus configured for improved data management for a two-terminal memory array is described herein. By way of example, disclosed embodiments relate to page management and transfer of data between page-sized subsets of a page buffer, and respective pages within one or more memory banks of the two-terminal memory array. The memory apparatus can emulate a larger page size than a physical page buffer utilized by the memory apparatus, to provide compatibility with different page size defaults while lowering current consumption by the page buffer. This can facilitate large or small array operations, taking advantage of higher efficiencies of two-terminal memory devices. In addition, page buffer data management can facilitate interleaved data transfers among multiple banks of memory, facilitating large memory capacities for a disclosed memory apparatus.

9. 发明授权

US10749529B2 Memory device including integrated deterministic pattern recognition circuitry 有权
公开(公告)号：US10749529B2
公开(公告)日：2020-08-18
申请号：US16368156
申请日：2019-03-28
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari
IPC分类号： G11C11/00 , H03K19/1776 , G06F1/10 , H03K19/17736 , G11C13/00
摘要： Various embodiments of the present disclosure provide for a memory device having inline processing circuitry. Disclosed memory devices can comprise logic circuits incorporating pattern recognition algorithms, in an embodiment. Comparative analysis functions on sets of data can be implemented with pulldown circuits connected to a common data line. In some embodiments, minimum values, maximum values and the like can be determined among the sets of data in a number of clock cycles comparable to a number of bits in the sets of data.

10. 发明授权

US10489700B1 Neuromorphic logic for an array of high on/off ratio non-volatile memory cells 有权
公开(公告)号：US10489700B1
公开(公告)日：2019-11-26
申请号：US14793156
申请日：2015-07-07
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari , Tanmay Kumar , Hagop Nazarian , Sung Hyun Jo
IPC分类号： G06N3/04 , G11C13/00
CPC分类号： G06N3/04 , G11C13/0069
摘要： Various embodiments disclosed herein provide for a neuromorphic logic system, comprising a bitline and a set of wordlines. The neuromorphic logic system also includes a set of resistive switching memory cells, respectively comprising a two-terminal volatile switching device and a two-terminal non-volatile memory device, at each intersection between the bit line and the set of wordlines, wherein the set of resistive switching memory cells are programmed to a set of resistive states and receive a voltage on the bitline above an activation threshold and wherein the magnitude of the voltage applied to the bitline corresponds to a magnitude of a sensory input, resulting in a current that corresponds to the magnitude of the sensor input and the set of resistive states.

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