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1. 发明授权

US10733107B2 Non-volatile memory apparatus and address classification method thereof 有权
公开(公告)号：US10733107B2
公开(公告)日：2020-08-04
申请号：US15287743
申请日：2016-10-07
申请人： VIA Technologies, Inc.
发明人： Ying-Yu Tai , Jiangli Zhu , Jiin Lai
IPC分类号： G06F12/10 , G06F12/1009 , G06F3/06 , G06F12/02
摘要： A non-volatile memory (NVM) apparatus and an address classification method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller accesses the NVM in accordance with a write command of a host. The controller may perform the address classification method. The address classification method includes: providing a data look-up table, wherein the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is a hot data address based on the corresponding counter value and the corresponding timer value.

2. 发明授权

US09009380B2 USB transaction translator with SOF timer and USB transaction translation method for periodically sending SOF packet 有权
标题翻译：具有SOF定时器的USB事务转换器和用于周期性发送SOF数据包的USB事务转换方法
公开(公告)号：US09009380B2
公开(公告)日：2015-04-14
申请号：US14038717
申请日：2013-09-26
申请人： VIA Technologies, Inc.
发明人： Jiin Lai , Chin-Sung Hsu , Terrance Shiyang Shih , Jinkuan Tang , Buheng Xu , Hui Jiang
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4059
摘要： A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.
摘要翻译：提供通用串行总线（USB）事务转换器以及微帧同步方法。设备接口经由设备总线耦合到设备，并且主机接口经由主机总线耦合到主机。至少两个缓冲区被配置为存储数据。控制器交替地将数据存储在缓冲器中。使用起始帧（SOF）计数器对SOF数据包进行计数，将SOF计数器的计数值与预定义的值进行比较。具体地说，当计数值达到或超过预定值时，控制器复位用于发送SOF分组的SOF定时器，使得来自主机的SOF分组和等时时间戳分组（ITP）同时被发送。此外，控制器根据来自主机的ITP延迟SOF分组的发送一段时间。

3. 发明授权

US11500801B2 Computing apparatus utilizing programmable logic circuit to implement direct memory access engine and at least one physical engine and providing data to be processed to at least one physical engine through direct memory access engine 有权
公开(公告)号：US11500801B2
公开(公告)日：2022-11-15
申请号：US17189176
申请日：2021-03-01
申请人： VIA Technologies Inc.
发明人： Yi-Lin Lai , Jiin Lai , Chin-Yin Tsai
IPC分类号： G06F13/28 , G06F13/16 , H04L67/1097 , H04L67/00 , G06F15/78
摘要： A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.

4. 发明申请

US20210303494A1 COMPUTING APPARATUS UTILIZING PROGRAMMABLE LOGIC CIRCUIT TO IMPLEMENT DIRECT MEMORY ACCESS ENGINE AND AT LEAST ONE PHYSICAL ENGINE AND PROVIDING DATA TO BE PROCESSED TO AT LEAST ONE PHYSICAL ENGINE THROUGH DIRECT MEMORY ACCESS ENGINE 有权
公开(公告)号：US20210303494A1
公开(公告)日：2021-09-30
申请号：US17189176
申请日：2021-03-01
申请人： VIA Technologies Inc.
发明人： Yi-Lin Lai , Jiin Lai , Chin-Yin Tsai
IPC分类号： G06F13/28 , G06F13/16 , H04L29/08
摘要： A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.

5. 发明授权

US11442882B2 Bridge circuit for providing conversion between PCIe-NVMe protocol and NVMe-TCP protocol and computer system using the same 有权
公开(公告)号：US11442882B2
公开(公告)日：2022-09-13
申请号：US17234751
申请日：2021-04-19
申请人： VIA Technologies Inc.
发明人： Jiin Lai
IPC分类号： G06F13/40 , G06F13/16 , G06F13/42 , H04L69/16
摘要： A bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is arranged to communicate with a host via a PCIe bus. The network subsystem is arranged to communicate with an NVMe-TCP device via a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is arranged to deal with data transfer associated with the NVMe-TCP device without intervention of the host.

6. 发明申请

US20210303338A1 COMPUTING APPARATUS AND DATA PROCESSING METHOD FOR OFFLOADING DATA PROCESSING OF DATA PROCESSING TASK FROM AT LEAST ONE GENERAL PURPOSE PROCESSOR 有权
公开(公告)号：US20210303338A1
公开(公告)日：2021-09-30
申请号：US17180882
申请日：2021-02-22
申请人： VIA Technologies Inc.
发明人： Jiin Lai
IPC分类号： G06F9/48 , G06F9/38 , G06F9/54 , H04L12/801 , H04L29/06
摘要： A computing apparatus includes at least one general purpose processor, at least one coprocessor, and at least one application specific processor. The at least one general purpose processor is arranged to run an application, wherein data processing of at least a portion of a data processing task is offloaded from the application running on the at least one general purpose processor. The at least one coprocessor is arranged to deal with a control flow of the data processing without intervention of the application running on the at least one general purpose processor. The at least one application specific processor is arranged to deal with a data flow of the data processing without intervention of the application running on the at least one general purpose processor.

7. 发明授权

US08930599B2 Data transmission system and method thereof 有权
标题翻译：数据传输系统及其方法
公开(公告)号：US08930599B2
公开(公告)日：2015-01-06
申请号：US14048388
申请日：2013-10-08
申请人： Via Technologies, Inc.
发明人： Jiin Lai , Buheng Xu , Jinkuan Tang
IPC分类号： G06F13/12 , G06F13/38 , G06F13/00 , G06F11/08
CPC分类号： G06F13/385 , G06F11/08 , G06F13/00 , G06F13/12
摘要： A data transmission system and method are provided. The data transmission method receives a second format data packet sent by a host; decodes the second format data packet sent by the host, and translating the decoded second format data packet into a first format data packet; transmits the first format data packet to a first device; receives a transmission response sent by the first device in response to the first format data packet, determines whether to transmit the transmission response to the host, and performs a re-try flow when the transmission response does not need to be transmitted to the host. Preferably, a data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device, and the second format data packet is consistent with the second device.
摘要翻译：提供了一种数据传输系统和方法。数据传输方法接收主机发送的第二格式数据包; 解码由主机发送的第二格式数据分组，并将解码的第二格式数据分组转换为第一格式数据分组; 将第一格式数据分组发送到第一设备; 响应于第一格式数据分组接收由第一设备发送的传输响应，确定是否向主机发送传输响应，并且当传输响应不需要发送到主机时执行重试流程。优选地，第一设备的数据传输速率比第二设备的数据传输速率慢，并且数据传输系统向后兼容于第一设备，并且第二格式数据分组与第二设备一致。

8. 发明授权

US08909820B2 Data transmission methods and hub devices utilizing the same 有权
标题翻译：数据传输方法和利用其的集线器设备
公开(公告)号：US08909820B2
公开(公告)日：2014-12-09
申请号：US13716765
申请日：2012-12-17
申请人： Via Technologies, Inc.
发明人： Jiin Lai , Jinkuan Tang
IPC分类号： G06F3/00 , G06F5/00 , G06F13/38 , G06F11/30
CPC分类号： G06F11/3068 , G06F13/1684 , G06F13/385
摘要： A hub device includes an upstream port, multiple downstream ports, a first and a second sub-hub module, a data-format detector, a transaction translator, and a controller. The upstream port is coupled to a host device supporting a first and/or a second data format. Each downstream port is coupled to one of a plurality of slave devices supporting a first and/or a second data format. The first sub-hub module supports transmission of data in the first data format. The second sub-hub module supports transmission of data in the second data format. The data-format detector detects the data format supported by the host device and the slave devices. The transaction translator transforms the data format between the first data format and the second data format. The controller determines whether to control the transaction translator to perform data-format transformation.
摘要翻译：集线器设备包括上游端口，多个下游端口，第一和第二子集线器模块，数据格式检测器，事务转换器和控制器。上游端口耦合到支持第一和/或第二数据格式的主机设备。每个下游端口耦合到支持第一和/或第二数据格式的多个从设备中的一个。第一子集线器模块支持以第一数据格式传输数据。第二子集线器模块支持以第二数据格式传输数据。数据格式检测器检测主机设备和从设备支持的数据格式。事务转换器将数据格式转换为第一数据格式和第二数据格式。控制器确定是否控制事务转换器执行数据格式转换。

9. 发明申请

US20210342287A1 BRIDGE CIRCUIT FOR PROVIDING CONVERSION BETWEEN PCIE-NVME PROTOCOL AND NVME-TCP PROTOCOL AND COMPUTER SYSTEM USING THE SAME 有权
公开(公告)号：US20210342287A1
公开(公告)日：2021-11-04
申请号：US17234751
申请日：2021-04-19
申请人： VIA Technologies Inc.
发明人： Jiin Lai
IPC分类号： G06F13/40 , G06F13/16 , G06F13/42 , H04L29/06
摘要： A bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is arranged to communicate with a host via a PCIe bus. The network subsystem is arranged to communicate with an NVMe-TCP device via a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is arranged to deal with data transfer associated with the NVMe-TCP device without intervention of the host.

10. 发明授权

US10055288B2 Controller device and operation method for non-volatile memory with 3-dimensional architecture 有权
公开(公告)号：US10055288B2
公开(公告)日：2018-08-21
申请号：US15225846
申请日：2016-08-02
申请人： VIA Technologies, Inc.
发明人： Ying Yu Tai , Jiin Lai , Jiangli Zhu
IPC分类号： H03M13/00 , G06F11/10 , G06F3/06 , G11C16/04 , G11C29/04
CPC分类号： G06F11/1072 , G06F3/0608 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0688 , G06F11/1068 , G11C16/0483 , G11C2029/0409 , G11C2029/0411
摘要： A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.

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