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1. 发明申请

US20140062563A1 CONTROLLING IMPEDANCE OF A SWITCH USING HIGH IMPEDANCE VOLTAGE SOURCES TO PROVIDE MORE EFFICIENT CLOCKING 有权
标题翻译：使用高阻抗电压源开关的控制阻抗提供更有效的时钟
公开(公告)号：US20140062563A1
公开(公告)日：2014-03-06
申请号：US13601155
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger
发明人： Visvesh S. Sathe , Samuel D. Naffziger
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F1/04
摘要： A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.
摘要翻译：集成电路的时钟系统包括形成开关的第一和第二晶体管，该开关用于在谐振工作模式和非谐振工作模式之间切换时钟系统。电感器在谐振模式下形成具有时钟系统的电容的谐振电路。当开关闭合时，开关接收时钟信号并将时钟信号提供给电感器，当开关断开时，断开电感与时钟系统的连接。第一和第二高阻抗电压源向开关提供相应的第一和第二电压，并且第一晶体管的栅极电压以围绕第一电压的时钟信号转变，并且第二晶体管的栅极电压以围绕第二电压的时钟信号转变使得对于第一和第二晶体管保持接近恒定的过驱动电压。

2. 发明授权

US08975936B2 Constraining clock skew in a resonant clocked system 有权
标题翻译：在谐振时钟系统中约束时钟偏移
公开(公告)号：US08975936B2
公开(公告)日：2015-03-10
申请号：US13601119
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger
发明人： Visvesh S. Sathe , Samuel D. Naffziger
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.
摘要翻译：集成电路包括谐振时钟网络的多个谐振时钟域。每个谐振时钟域具有至少一个时钟驱动器，其将一部分时钟信号提供给相关联的谐振时钟域。谐振时钟网络以谐振模式工作，其中电感器连接到谐振时钟域之间边界处的谐振时钟域对。每个电感器在电感器所连接的一对谐振时钟域中形成具有时钟负载电容的LC电路。

3. 发明授权

US08854100B2 Clock driver for frequency-scalable systems 有权
标题翻译：用于频率可伸缩系统的时钟驱动器
公开(公告)号：US08854100B2
公开(公告)日：2014-10-07
申请号：US13601188
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger , Srikanth Arekapudi
发明人： Visvesh S. Sathe , Samuel D. Naffziger , Srikanth Arekapudi
IPC分类号： G06F1/04 , H03K3/00 , H03K19/003
CPC分类号： H03K19/003 , G06F1/10
摘要： A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.
摘要翻译：用于谐振时钟网络的时钟驱动器包括接收并提供延迟的时钟信号的延迟电路。第一晶体管被耦合以接收第一脉冲控制信号并提供时钟驱动器的输出时钟节点。第一控制信号的有效边沿响应延迟的时钟信号的下降沿。第二晶体管被耦合以接收第二控制信号并提供时钟驱动器的输出时钟节点。第二控制信号的有效边沿响应延迟的时钟信号的上升沿。

4. 发明授权

US08193799B2 Interposer including voltage regulator and method therefor 有权
标题翻译：内插器包括电压调节器及其方法
公开(公告)号：US08193799B2
公开(公告)日：2012-06-05
申请号：US12236003
申请日：2008-09-23
申请人： Stephen V. Kosonocky , Samuel D. Naffziger , Visvesh S. Sathe
发明人： Stephen V. Kosonocky , Samuel D. Naffziger , Visvesh S. Sathe
IPC分类号： B23K11/24
CPC分类号： H01L25/16 , H01L25/0657 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H05K1/0262 , H05K2201/10378 , Y10T307/406 , H01L2224/0401
摘要： A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.
摘要翻译：公开了一种包括被称为集成电路插入器的电子设备的装置。集成电路包括电压调节器模块。插入器附接到诸如另一集成电路的电子设备，并且便于对电子设备的电力的控制和分配。集成电路插入器还可以在附接的电子设备和另一电子设备之间进行信令。集成电路插入器上的电压调节器模块可以被配置为向附接的电子设备提供电压参考信号。根据电子设备的工作要求，可以使能或禁止由集成电路插入器产生电压参考信号，并且可以调节电压参考信号的值。

5. 发明授权

US08836403B2 Programmable clock driver 有权
标题翻译：可编程时钟驱动
公开(公告)号：US08836403B2
公开(公告)日：2014-09-16
申请号：US13601175
申请日：2012-08-31
申请人： Visvesh S. Sathe , Srikanth Arekapudi , Samuel D. Naffziger , Manivannan Bhoopathy
发明人： Visvesh S. Sathe , Srikanth Arekapudi , Samuel D. Naffziger , Manivannan Bhoopathy
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength.
摘要翻译：时钟驱动器电路提供具有根据提供给时钟驱动器的一个或多个控制信号确定的驱动强度的时钟信号，该时钟驱动器在运行时间内变化。时钟驱动器以相关时钟网络的非谐振工作模式的第一驱动强度和相关时钟网络的谐振工作模式下的第二驱动强度操作，第一驱动强度高于第二驱动强度驱动力。

6. 发明申请

US20140062565A1 CLOCK DRIVER FOR FREQUENCY-SCALABLE SYSTEMS 有权
标题翻译：频率可调系统的时钟驱动器
公开(公告)号：US20140062565A1
公开(公告)日：2014-03-06
申请号：US13601188
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger , Srikanth Arekapudi
发明人： Visvesh S. Sathe , Samuel D. Naffziger , Srikanth Arekapudi
IPC分类号： G06F1/04
CPC分类号： H03K19/003 , G06F1/10
摘要： A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.
摘要翻译：用于谐振时钟网络的时钟驱动器包括接收并提供延迟的时钟信号的延迟电路。第一晶体管被耦合以接收第一脉冲控制信号并提供时钟驱动器的输出时钟节点。第一控制信号的有效边沿响应延迟的时钟信号的下降沿。第二晶体管被耦合以接收第二控制信号并提供时钟驱动器的输出时钟节点。第二控制信号的有效边沿响应延迟的时钟信号的上升沿。

7. 发明申请

US20140062562A1 CONSTRAINING CLOCK SKEW IN A RESONANT CLOCKED SYSTEM 有权
标题翻译：在时钟系统中约束时钟
公开(公告)号：US20140062562A1
公开(公告)日：2014-03-06
申请号：US13601119
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger
发明人： Visvesh S. Sathe , Samuel D. Naffziger
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.
摘要翻译：集成电路包括谐振时钟网络的多个谐振时钟域。每个谐振时钟域具有至少一个时钟驱动器，其将一部分时钟信号提供给相关联的谐振时钟域。谐振时钟网络以谐振模式工作，其中电感器连接到谐振时钟域之间边界处的谐振时钟域对。每个电感器在电感器所连接的一对谐振时钟域中形成具有时钟负载电容的LC电路。

8. 发明申请

US20120154188A1 SENSE-AMPLIFIER MONOTIZER 有权
公开(公告)号：US20120154188A1
公开(公告)日：2012-06-21
申请号：US12974203
申请日：2010-12-21
申请人： Samuel D. Naffziger , Visvesh S. Sathe , Srikanth Arekapudi
发明人： Samuel D. Naffziger , Visvesh S. Sathe , Srikanth Arekapudi
IPC分类号： H03M99/00 , H03F3/45
CPC分类号： G11C7/065
摘要： A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase.
摘要翻译：感测放大器单调器包括放大器电路和保持器电路。当时钟信号处于第一阶段时，放大器电路输出预定的逻辑状态，并对数据信号进行采样，并且在时钟信号处于第二阶段时输出数据信号和互补逻辑状态中的至少一个数据信号。一旦数据信号在时钟信号处于第二阶段被采样时，数据信号的随后变化就不影响放大器电路的输出。一旦在时钟信号处于第二阶段，数据信号被采样，保持器电路将保持采样数据信号的逻辑状态。放大器电路可以接收多个数据信号，并且在时钟信号处于第二阶段时输出由选择信号选择的数据信号和/或互补值。

9. 发明授权

US08742817B2 Controlling impedance of a switch using high impedance voltage sources to provide more efficient clocking 有权
标题翻译：使用高阻抗电压源控制开关的阻抗，以提供更有效的时钟
公开(公告)号：US08742817B2
公开(公告)日：2014-06-03
申请号：US13601155
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger
发明人： Visvesh S. Sathe , Samuel D. Naffziger
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10 , G06F1/04
摘要： A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.
摘要翻译：集成电路的时钟系统包括形成开关的第一和第二晶体管，该开关用于在谐振工作模式和非谐振工作模式之间切换时钟系统。电感器在谐振模式下形成具有时钟系统的电容的谐振电路。当开关闭合时，开关接收时钟信号并将时钟信号提供给电感器，当开关断开时，断开电感与时钟系统的连接。第一和第二高阻抗电压源向开关提供相应的第一和第二电压，并且第一晶体管的栅极电压以围绕第一电压的时钟信号转变，并且第二晶体管的栅极电压以围绕第二电压的时钟信号转变使得对于第一和第二晶体管保持接近恒定的过驱动电压。

10. 发明授权

US08710868B2 Sense-amplifier monotizer 有权
标题翻译：感应放大器单调器
公开(公告)号：US08710868B2
公开(公告)日：2014-04-29
申请号：US12974203
申请日：2010-12-21
申请人： Samuel D. Naffziger , Visvesh S. Sathe , Srikanth Arekapudi
发明人： Samuel D. Naffziger , Visvesh S. Sathe , Srikanth Arekapudi
IPC分类号： G11C7/00
CPC分类号： G11C7/065
摘要： A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase.
摘要翻译：感测放大器单调器包括放大器电路和保持器电路。当时钟信号处于第一阶段时，放大器电路输出预定的逻辑状态，并对数据信号进行采样，并且在时钟信号处于第二阶段时输出数据信号和互补逻辑状态中的至少一个数据信号。一旦数据信号在时钟信号处于第二阶段被采样时，数据信号的随后变化就不影响放大器电路的输出。一旦在时钟信号处于第二阶段，数据信号被采样，保持器电路将保持采样数据信号的逻辑状态。放大器电路可以接收多个数据信号，并且在时钟信号处于第二阶段时输出由选择信号选择的数据信号和/或互补值。

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