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1. 发明授权

US08767440B2 Sector array addressing for ECC management 有权
标题翻译： ECC管理的扇区阵列寻址
公开(公告)号：US08767440B2
公开(公告)日：2014-07-01
申请号：US13892499
申请日：2013-05-13
申请人： Ward Parkinson , Thomas Trent
发明人： Ward Parkinson , Thomas Trent
IPC分类号： G11C11/00
CPC分类号： G11C13/0033 , G11C11/22 , G11C13/0023
摘要： An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.
摘要翻译：一种具有管理误差校正需求的短路缺陷的非易失性存储器阵列的寻址方案。该方案通常避免在写入期间同时主动驱动所选单元的行线和列线。相反，只有单行或列行在任何一个时间被主动驱动，所有其他的数组行都是浮动的。此外，可以限制在取出期间从给定的行或列访问的存储器单元的数量。该方案的优点包括防止短路引起阵列过剩的电流，并将由短路引起的读或写故障的频率限制在可管理的数量上。在一个实施例中，该方案将对错误校正的需求保持在闪存控制器的纠错能力内。示例性实施例包括相变存储器阵列。

2. 发明申请

US20120069622A1 Sector Array Addressing for ECC Management 有权
标题翻译： ECC管理的扇区阵列寻址
公开(公告)号：US20120069622A1
公开(公告)日：2012-03-22
申请号：US12884413
申请日：2010-09-17
申请人： Ward Parkinson , Thomas Trent
发明人： Ward Parkinson , Thomas Trent
IPC分类号： G11C11/22 , G11C7/00 , G11C11/00
CPC分类号： G11C13/0033 , G11C11/22 , G11C13/0023
摘要： An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.
摘要翻译：一种具有管理误差校正需求的短路缺陷的非易失性存储器阵列的寻址方案。该方案通常避免在写入期间同时主动驱动所选单元的行线和列线。相反，只有单行或列行在任何一个时间被主动驱动，所有其他的数组行都是浮动的。此外，可以限制在取出期间从给定的行或列访问的存储器单元的数量。该方案的好处包括防止短路引起阵列过剩的电流，并将由短路导致的读或写故障的频率限制在可管理的数量上。在一个实施例中，该方案将对错误校正的需求保持在闪存控制器的纠错能力内。示例性实施例包括相变存储器阵列。

3. 发明申请

US20130250648A1 Sector Array Addressing for ECC Management 有权
标题翻译： ECC管理的扇区阵列寻址
公开(公告)号：US20130250648A1
公开(公告)日：2013-09-26
申请号：US13892499
申请日：2013-05-13
申请人： Ward Parkinson , Thomas Trent
发明人： Ward Parkinson , Thomas Trent
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C11/22 , G11C13/0023
摘要： An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.
摘要翻译：一种具有管理误差校正需求的短路缺陷的非易失性存储器阵列的寻址方案。该方案通常避免在写入期间同时主动驱动所选单元的行线和列线。相反，只有单行或列行在任何一个时间被主动驱动，所有其他的数组行都是浮动的。此外，可以限制在取出期间从给定的行或列访问的存储器单元的数量。该方案的好处包括防止短路引起阵列过剩的电流，并将由短路导致的读或写故障的频率限制在可管理的数量上。在一个实施例中，该方案将对错误校正的需求保持在闪存控制器的纠错能力内。示例性实施例包括相变存储器阵列。

4. 发明授权

US08441836B2 Sector array addressing for ECC management 有权
标题翻译： ECC管理的扇区阵列寻址
公开(公告)号：US08441836B2
公开(公告)日：2013-05-14
申请号：US12884413
申请日：2010-09-17
申请人： Ward Parkinson , Thomas Trent
发明人： Ward Parkinson , Thomas Trent
IPC分类号： G11C11/00
CPC分类号： G11C13/0033 , G11C11/22 , G11C13/0023
摘要： An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.
摘要翻译：一种具有管理误差校正需求的短路缺陷的非易失性存储器阵列的寻址方案。该方案通常避免在写入期间同时主动驱动所选单元的行线和列线。相反，只有单行或列行在任何一个时间被主动驱动，所有其他的数组行都是浮动的。此外，可以限制在取出期间从给定的行或列访问的存储器单元的数量。该方案的好处包括防止短路引起阵列过剩的电流，并将由短路导致的读或写故障的频率限制在可管理的数量上。在一个实施例中，该方案将对错误校正的需求保持在闪存控制器的纠错能力内。示例性实施例包括相变存储器阵列。

5. 发明授权

US09472273B2 Method and apparatus for decoding memory 有权
公开(公告)号：US09472273B2
公开(公告)日：2016-10-18
申请号：US14791463
申请日：2015-07-05
申请人： Ward Parkinson
发明人： Ward Parkinson
IPC分类号： G11C8/10 , G11C13/00 , G11C8/08
CPC分类号： G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/76
摘要： A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

6. 发明申请

US20120051140A1 RAM memory device with NAND type interface 有权
标题翻译：具有NAND型接口的RAM存储器件
公开(公告)号：US20120051140A1
公开(公告)日：2012-03-01
申请号：US13199328
申请日：2011-08-26
申请人： Steven Jeffrey Grossman , Ward Parkinson , Daniel Robert Shepard , Thomas Michael Trent , Sam Ira Young
发明人： Steven Jeffrey Grossman , Ward Parkinson , Daniel Robert Shepard , Thomas Michael Trent , Sam Ira Young
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/10 , G11C13/0002
摘要： A random access memory device is disclosed having an interface that is compatible with a NAND FLASH memory device such that the device can be operated with a standard NAND memory device's controller device. This memory device is can store data internally using any random access storage technology including PRAM, MRAM, RRAM, FRAM, OTP-RAM and 3-D memory.
摘要翻译：公开了一种随机存取存储器件，其具有与NAND FLASH存储器件兼容的接口，使得该器件可以与标准NAND存储器件的控制器器件一起工作。该存储器件可以使用包括PRAM，MRAM，RRAM，FRAM，OTP-RAM和3-D存储器在内的任何随机存取技术在内部存储数据。

7. 发明申请

US20110240943A1 Immunity of Phase Change Material to Disturb in the Amorphous Phase 有权
标题翻译：相变材料在无定形相中干扰的抗扰度
公开(公告)号：US20110240943A1
公开(公告)日：2011-10-06
申请号：US13158565
申请日：2011-06-13
申请人： George Gordon , Semyon D. Savransky , Ward Parkinson , Sergey A. Kostylev , James Reed , Tyler Lowrey , Ilya V. Karpov , Gianpaolo Spadini
发明人： George Gordon , Semyon D. Savransky , Ward Parkinson , Sergey A. Kostylev , James Reed , Tyler Lowrey , Ilya V. Karpov , Gianpaolo Spadini
IPC分类号： H01L45/00
CPC分类号： G11C13/0033 , G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/0035 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/3431 , G11C29/04 , G11C2013/0052 , G11C2013/0078 , G11C2013/0092 , G11C2213/76
摘要： Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.
摘要翻译：通过在对相变存储器中的复位状态进行编程时产生基本上不含结晶核的非晶相，可以减小从复位到设定状态的干扰。在一些实施例中，这可以通过使用超过相变存储元件的阈值电压的电流或电压来实现，但不超过将导致干扰的安全电流电压来实现。

8. 发明授权

US07839674B2 Programmable matrix array with chalcogenide material 有权
标题翻译：具有硫属化物材料的可编程矩阵阵列
公开(公告)号：US07839674B2
公开(公告)日：2010-11-23
申请号：US12286784
申请日：2008-10-02
申请人： Tyler Lowrey , Ward Parkinson , Guy Wicker
发明人： Tyler Lowrey , Ward Parkinson , Guy Wicker
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/72 , G11C2213/75 , G11C2213/76 , G11C2213/79 , H01L27/2427
摘要： A chalcogenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.
摘要翻译：提出硫族化物材料来编程电可编程矩阵阵列的交叉连接晶体管耦合互连线。可以通过选择性地将薄绝缘击穿层与选择装置或相变材料串联来减小泄漏。矩阵阵列可以用在可编程逻辑器件中。

9. 发明申请

US20100110782A1 Page Mode Access for Non-volatile Memory Arrays 有权
标题翻译：页面模式访问非易失性存储器阵列
公开(公告)号：US20100110782A1
公开(公告)日：2010-05-06
申请号：US12683735
申请日：2010-01-07
申请人： Ward Parkinson , Yukio Fuji
发明人： Ward Parkinson , Yukio Fuji
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1021 , G11C7/065 , G11C7/08 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C7/22 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C16/3431 , G11C2013/0085 , G11C2207/005
摘要： An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.
摘要翻译：布置在逻辑列和逻辑行中的非易失性存储器单元的阵列，以及相关联的电路，以使得能够并行地读取或写入行上的一个或多个存储器单元。在一些实施例中，存储器单元阵列可以包括相变材料。在一些实施例中，电路可以包括写入驱动器，读取驱动器，读出放大器以及通过扩展刷新来将存储器单元与读出放大器隔离的电路。

10. 发明授权

US07706178B2 Programmable matrix array with phase-change material 有权
标题翻译：具相变材料的可编程矩阵阵列
公开(公告)号：US07706178B2
公开(公告)日：2010-04-27
申请号：US12069092
申请日：2008-02-06
申请人： Ward Parkinson
发明人： Ward Parkinson
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/77 , H01L27/2463 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H03K19/17736 , Y10S438/90
摘要： A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The logic portions of the programmable logic device may be tri-stated.
摘要翻译：提出了一种相变材料用于将互连线耦合到电可编程矩阵阵列。可以通过在相变材料和至少一条线之间选择性地放置薄的绝缘击穿层来降低泄漏。矩阵阵列可以用在可编程逻辑器件中。可编程逻辑器件的逻辑部分可以是三态的。

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