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1. 发明授权

US09563259B2 Apparatus and method for activating and shutting down individual enhanced pipeline stages based on stage priority and performance requirements 有权
标题翻译：基于阶段优先级和性能要求激活和关闭各个增强流水线阶段的装置和方法
公开(公告)号：US09563259B2
公开(公告)日：2017-02-07
申请号：US12357910
申请日：2009-01-22
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F1/32 , G06F9/30 , G06F11/30 , G06F9/38 , G06F9/48
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种基于流水线的中央处理单元，其特征在于，根据功能，将流水线划分为基本流水线阶段和增强流水线阶段，基础流水线段同时被激活，而增强流水线阶段根据对工作负载的性能要求。本发明还公开了一种基于流水线的中央处理单元，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，每个流水线分段分为基本模块和至少一个增强模块，基模块为激活所有时间，增强模块根据工作负载的性能要求被激活或关闭。

2. 发明申请

US20090193424A1 METHOD OF PROCESSING INSTRUCTIONS IN PIPELINE-BASED PROCESSOR AND CORRESPONDING PROCESSOR 有权
标题翻译：基于管道处理器和相应处理器的处理指令的方法
公开(公告)号：US20090193424A1
公开(公告)日：2009-07-30
申请号：US12357910
申请日：2009-01-22
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F9/46
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

3. 发明申请

US20120210106A1 METHOD OF PROCESSING INSTRUCTIONS IN PIPELINE-BASED PROCESSOR 有权
标题翻译：基于管道处理器的处理指令的方法
公开(公告)号：US20120210106A1
公开(公告)日：2012-08-16
申请号：US13457011
申请日：2012-04-26
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F9/38
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

4. 发明申请

US20100161875A1 SIMULATOR AND SIMULATING METHOD FOR RUNNING GUEST PROGRAM IN HOST 有权
标题翻译：用于运行主机程序的模拟和模拟方法
公开(公告)号：US20100161875A1
公开(公告)日：2010-06-24
申请号：US12633299
申请日：2009-12-08
申请人： Xiao Tao Chang , Huayong Wang , Kun Wang , Yu Zhang
发明人： Xiao Tao Chang , Huayong Wang , Kun Wang , Yu Zhang
IPC分类号： G06F12/10 , G06F9/455 , G06F12/00
CPC分类号： G06F12/1036 , G06F9/4552 , G06F9/45554 , G06F9/45558 , G06F2009/45583
摘要： A Simulator and a simulating method for running a guest program in a host are disclosed. The simulator includes: an initialization device configured for setting content of a hypervisor page table in the host, the hypervisor page table mapping a guest physical address space to a host physical address space. The simulator further includes a binary translation device configured for employing a program logical address to perform a memory access in code translation. The simulator also includes a miss handling device configured for updating a guest translation look-aside buffer by treating a miss in a host translation look-aside buffer caused by the execution of the translated code as a miss in the guest translation look-aside buffer, wherein the host translation look-aside buffer is configured to buffer entries for mapping addresses in a guest program logical address space to addresses in the guest physical address space. The simulator further includes an update tracing device configured for, in response to the update to the guest translation look-aside buffer, perform the update to the host translation look-aside buffer. Also disclosed is a method for running a guest program in a host.
摘要翻译：公开了一种用于在主机中运行访客程序的模拟器和模拟方法。模拟器包括：配置用于设置主机中的管理程序页表的内容的初始化设备，将客户物理地址空间映射到主机物理地址空间的管理程序页表。仿真器还包括被配置为使用程序逻辑地址来执行代码转换中的存储器访问的二进制翻译装置。所述模拟器还包括未命中处理装置，其被配置为通过处理由所述翻译代码的执行而导致的主机翻译后备缓冲器中的未命中来更新客体翻译后备缓冲器，作为所述访客翻译后备缓冲器中的未命中，其中所述主机翻译后备缓冲器被配置为缓冲条目以将访客程序逻辑地址空间中的地址映射到所述访客物理地址空间中的地址。所述模拟器还包括更新跟踪装置，所述更新跟踪装置被配置为响应于所述客户端翻译后备缓冲器的更新，执行对所述主机翻译后备缓冲器的更新。还公开了一种在主机中运行客座程序的方法。

5. 发明授权

US08397050B2 Simulator and simulating method for running guest program in host 有权
标题翻译：在主机中运行客人程序的模拟器和模拟方法
公开(公告)号：US08397050B2
公开(公告)日：2013-03-12
申请号：US12633299
申请日：2009-12-08
申请人： Xiao Tao Chang , Huayong Wang , Kun Wang , Yu Zhang
发明人： Xiao Tao Chang , Huayong Wang , Kun Wang , Yu Zhang
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F9/4552 , G06F9/45554 , G06F9/45558 , G06F2009/45583
摘要： A Simulator and a simulating method for running a guest program in a host are disclosed. The simulator includes: an initialization device configured for setting content of a hypervisor page table in the host, the hypervisor page table mapping a guest physical address space to a host physical address space. The simulator further includes a binary translation device configured for employing a program logical address to perform a memory access in code translation. The simulator also includes a miss handling device configured for updating a guest translation look-aside buffer by treating a miss in a host translation look-aside buffer caused by the execution of the translated code as a miss in the guest translation look-aside buffer, wherein the host translation look-aside buffer is configured to buffer entries for mapping addresses in a guest program logical address space to addresses in the guest physical address space. The simulator further includes an update tracing device configured for, in response to the update to the guest translation look-aside buffer, perform the update to the host translation look-aside buffer. Also disclosed is a method for running a guest program in a host.
摘要翻译：公开了一种用于在主机中运行访客程序的模拟器和模拟方法。模拟器包括：配置用于设置主机中的管理程序页表的内容的初始化设备，将客户物理地址空间映射到主机物理地址空间的管理程序页表。仿真器还包括被配置为使用程序逻辑地址来执行代码转换中的存储器访问的二进制翻译装置。所述模拟器还包括未命中处理装置，其被配置为通过处理由所述翻译代码的执行而导致的主机翻译后备缓冲器中的未命中来更新客体翻译后备缓冲器，作为所述访客翻译后备缓冲器中的未命中，其中所述主机翻译后备缓冲器被配置为缓冲条目以将访客程序逻辑地址空间中的地址映射到所述访客物理地址空间中的地址。所述模拟器还包括更新跟踪装置，所述更新跟踪装置被配置为响应于所述客户端翻译后备缓冲器的更新，执行对所述主机翻译后备缓冲器的更新。还公开了一种在主机中运行客座程序的方法。

6. 发明申请

US20100217945A1 FAST CONTEXT SAVE IN TRANSACTIONAL MEMORY 审中-公开
标题翻译：快速的内容保存在交易记忆中
公开(公告)号：US20100217945A1
公开(公告)日：2010-08-26
申请号：US12708634
申请日：2010-02-19
申请人： Yi Ge , Rui Hou , Huayong Wang
发明人： Yi Ge , Rui Hou , Huayong Wang
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F9/30105 , G06F9/30116 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/3863 , G06F9/528
摘要： The present invention provides a method, apparatus and article of manufacture, for fast context saving in transactional memory. The method creates a mapping table that includes entries corresponding to architectural registers. Each entry includes a physical register index and shadow bit of a first physical register mapped to an architectural register. In response to a detection that an update occurs to an architectural register in a transaction and its shadow bit being an invalid value, the method sets the shadow bit to be a valid value and sets a shadow register for the architectural register using the physical register index of the first physical register. The method maps a second physical register to the shadow register in order to save a modified value generated by an update process and saves the original value before the update process by use of the first physical register corresponding to the architecture register.
摘要翻译：本发明提供了一种用于在事务存储器中快速上下文保存的方法，装置和制品。该方法创建一个包含对应于架构寄存器的条目的映射表。每个条目包括映射到架构寄存器的第一物理寄存器的物理寄存器索引和影像位。响应于检测到交易中的体系结构寄存器发生更新，并且其影子位是无效值，则该方法将阴影位设置为有效值，并使用物理寄存器索引为体系结构寄存器设置影子寄存器的第一个物理登记册。该方法将第二个物理寄存器映射到影子寄存器，以便保存由更新过程生成的修改值，并通过使用对应于架构寄存器的第一个物理寄存器在更新过程之前保存原始值。

7. 发明申请

US20120324038A1 Controlling Shared Memory 审中-公开
公开(公告)号：US20120324038A1
公开(公告)日：2012-12-20
申请号：US13599501
申请日：2012-08-30
申请人： Ying Chen , Yan Li , Qiming Teng , Huayong Wang
发明人： Ying Chen , Yan Li , Qiming Teng , Huayong Wang
IPC分类号： G06F15/167
CPC分类号： H04L49/901 , G06F9/544 , G06F15/167
摘要： In view of the characteristics of distributed applications, the present invention proposes a technical solution for applying a shared memory on an NIC comprising: a shared memory configured to provide shared storage space for a task of a distributed application, and a microcontroller. Furthermore, the present invention provides a computer device that includes the above-mentioned NIC, a method for controlling a read/write operation on a shared memory of a NIC, and a method for invoking the NIC. The use of the technical solution provided in the present invention bypasses the processing of network protocol stack, avoids the time delay introduced by the network protocol stack. The present invention does not need to perform TCP/IP encapsulation on the data packet, thus greatly saving additional packet header and packet tail overheads generated from the TCP/IP layer data encapsulation.

8. 发明申请

US20100186015A1 METHOD AND APPARATUS FOR IMPLEMENTING A TRANSACTIONAL STORE SYSTEM USING A HELPER THREAD 失效
标题翻译：使用帮助螺纹实现交易存储系统的方法和装置
公开(公告)号：US20100186015A1
公开(公告)日：2010-07-22
申请号：US12685863
申请日：2010-01-12
申请人： Huayong Wang
发明人： Huayong Wang
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F9/3842 , G06F9/3851 , G06F9/528
摘要： A method, apparatus, and computer readable article of manufacture for executing a transaction by a processor apparatus that includes a plurality of hardware threads. The method includes the steps of: creating a main software thread for executing the transaction; creating a helper software thread for executing a barrier function; executing the main software thread and the helper software thread using the plurality of hardware threads; deciding whether the execution of the barrier function is required; executing the barrier function by the helper software thread; and returning to the main software thread. The step of executing the barrier function includes: stalling the main software thread; activating the helper software thread; and exiting the helper software thread in response to completion of the execution.
摘要翻译：一种用于由包括多个硬件线程的处理器装置执行交易的方法，装置和计算机可读制品。该方法包括以下步骤：创建用于执行交易的主软件线程; 创建一个执行屏障功能的帮助软件线程; 使用多个硬件线程执行主软件线程和辅助软件线程; 决定是否需要执行屏障功能; 由助手软件线程执行屏障功能; 并返回主软件线程。执行屏障功能的步骤包括：停止主软件线程; 激活帮助软件线程; 并且响应于完成执行而退出帮助软件线程。

9. 发明授权

US08131894B2 Method and system for a sharing buffer 有权
标题翻译：共享缓冲区的方法和系统
公开(公告)号：US08131894B2
公开(公告)日：2012-03-06
申请号：US12623496
申请日：2009-11-23
申请人： Harold Wade Cain, III , Rui Hou , Xiaowei Shen , Huayong Wang
发明人： Harold Wade Cain, III , Rui Hou , Xiaowei Shen , Huayong Wang
IPC分类号： G06F13/12
CPC分类号： G06F9/30087 , G06F9/467 , G06F9/5016
摘要： A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.
摘要翻译：用于共享缓冲区管理的系统，方法和计算机可读制造品。该系统包括：预测器模块，用于根据交易的历史信息在运行时预测交易的交易数据大小; 以及资源管理模块，用于响应于所述事务的开始，根据预测的事务数据大小来分配所述事务的共享缓冲器资源，以响应所述事务的成功承诺来记录所述事务所占用的实际共享缓冲区大小;以及更新交易的历史信息。

10. 发明申请

US20100106950A1 METHOD AND SYSTEM FOR LOADING STATUS CONTROL OF DLL 有权
标题翻译：用于加载DLL的状态控制的方法和系统
公开(公告)号：US20100106950A1
公开(公告)日：2010-04-29
申请号：US12607241
申请日：2009-10-28
申请人： Rui Hou , Zhi Yu Liu , Huayong Wang , Yan Qi Wang
发明人： Rui Hou , Zhi Yu Liu , Huayong Wang , Yan Qi Wang
IPC分类号： G06F9/54 , G06F9/45 , G06F9/38 , G06F9/44
CPC分类号： G06F8/41 , G06F8/37 , G06F9/30058 , G06F9/44521 , G06F9/44594
摘要： Apparatus and methods are provided for controlling the loading status of DLLs. Specifically, a streaming program compiler is provided. The compiler includes operation modules for calling DLLs during streaming program execution; association table generating units for generating association tables according to user-defined rules, where the association table includes entries indicating (i) stream branches of the streaming program and (ii) an operation module corresponding to the stream branches; and a trigger generating unit for generating a trigger based on user-defined rules, where the trigger generating unit (i) determines which conditions for loading and unloading DLLs fit the streaming program, (ii) matches these conditions to a particular stream branch to identify a matched stream branch, and (iii) sends out triggering signals indicating the matched stream branch. This invention also provides a corresponding method and controller.
摘要翻译：提供了用于控制DLL的加载状态的装置和方法。具体地说，提供流程序编译器。编译器包括在流程序执行期间调用DLL的操作模块; 关联表生成单元，用于根据用户定义的规则生成关联表，其中所述关联表包括指示（i）流程序流的流分支和（ii）对应于流分支的操作模块的条目; 触发器生成单元，用于基于用户定义的规则生成触发，其中触发器生成单元（i）确定用于加载和卸载DLL的条件适合于流程序，（ii）将这些条件与特定流分支相匹配以识别匹配流分支，以及（iii）发出指示匹配流分支的触发信号。本发明还提供了相应的方法和控制器。

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