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1. 发明申请

US20140104950A1 NON-VOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20140104950A1
公开(公告)日：2014-04-17
申请号：US14027926
申请日：2013-09-16
申请人： Winbond Electronics Corp.
发明人： Masaru YANO
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/10 , G11C16/3454
摘要： A non-volatile semiconductor memory includes a memory array. In a programming operation, programming pulses are applied to a page of the memory array to program data to the page. In an erase operation, erase pulses are applied to a block of the memory array to erase data in the block. The non-volatile semiconductor memory performs a pre-program operation before the erase operation and a post-erase operation after the erase operation. In the pre-program operation, each page of the block is programmed according to voltage information relating programming pulses. In the erase operation, data in the block is erased according to the voltage information relating programming pulses.
摘要翻译：非易失性半导体存储器包括存储器阵列。在编程操作中，将编程脉冲施加到存储器阵列的页面以将数据编程到页面。在擦除操作中，擦除脉冲被施加到存储器阵列的块以擦除块中的数据。非易失性半导体存储器在擦除操作之前进行预编程操作，并且在擦除操作之后执行擦除后操作。在预编程操作中，根据与编程脉冲相关的电压信息对块的每一页进行编程。在擦除操作中，根据与编程脉冲相关的电压信息擦除块中的数据。

2. 发明申请

US20210210553A1 RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20210210553A1
公开(公告)日：2021-07-08
申请号：US17133891
申请日：2020-12-24
申请人： Winbond Electronics Corp.
发明人： Masaru YANO
IPC分类号： H01L27/24 , H01L45/00 , G11C13/00
摘要： Provide a resistive random-access memory device having an optimized 3D construction. A resistive random-access memory includes a plurality of pillars, a plurality of bit lines, and a memory cell. The pillars extend vertically along the main surface of the substrate. The bit lines extend in a horizontal direction. The memory cell is formed at the intersection of the pillars and the bit lines. The memory cell includes a gate insulating film, a semiconductor film, and a resistive element. The gate insulating film is formed on the circumference of the pillar. The semiconductor film is formed on the circumference of gate insulating film and provides a channel area. The resistive element is formed on the circumference of the semiconductor film. A first electrode area on the circumference of the resistive element and a second electrode area facing the first electrode area are electrically connected to a pair of adjacent bit lines.

3. 发明申请

US20170373015A1 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND GENERATION METHOD OF UNIQUE INFORMATION 审中-公开
公开(公告)号：US20170373015A1
公开(公告)日：2017-12-28
申请号：US15631889
申请日：2017-06-23
申请人： Winbond Electronics Corp.
发明人： Masaru YANO , Pin-Yao WANG
IPC分类号： H01L23/544 , H01L21/66 , G11C16/22 , H01L23/00 , G05B19/12
CPC分类号： H01L23/544 , G05B19/128 , G11C16/22 , H01L22/20 , H01L24/49 , H01L2223/5444
摘要： A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.

4. 发明申请

US20170047123A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其擦除方法
公开(公告)号：US20170047123A1
公开(公告)日：2017-02-16
申请号：US15233231
申请日：2016-08-10
申请人： Winbond Electronics Corp.
发明人： Masaru YANO
IPC分类号： G11C16/34 , G11C16/14 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/14 , G11C16/3472
摘要： Provided is an erase method for a non-volatile semiconductor memory device to compensate for the change in property of a memory cell, in proportion to the number of data rewrites to the memory cell. The erase method has an erase step to erase charges of a charge accumulation layer by applying an erase voltage to a channel region of a selected memory cell, and a soft-programming step to perform soft-programming to the charges in the accumulation layer by virtue of applying a soft-programming voltage which is smaller than a programming voltage to program the memory cell. The erase voltage is increased step by step when it is applied repeatedly. The soft-programming voltage is decreased step by step when it is applied repeatedly.
摘要翻译：提供了一种用于非易失性半导体存储器件的擦除方法，以与存储器单元的数据重写数量成比例地补偿存储器单元的性能变化。擦除方法具有擦除步骤，通过向所选择的存储单元的沟道区域施加擦除电压来擦除电荷累积层的电荷，以及软编程步骤，通过以下方式对积累层中的电荷进行软编程施加小于编程电压的软编程电压来对存储单元进行编程。当反复施加时，擦除电压逐步增加。反复施加时，软编程电压逐步降低。

5. 发明申请

US20150311354A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20150311354A1
公开(公告)日：2015-10-29
申请号：US14263536
申请日：2014-04-28
申请人： Winbond Electronics Corp.
发明人： Masaru YANO , Hiroki MURAKAMI
IPC分类号： H01L29/8605 , G05F1/575
CPC分类号： G05F1/575 , H01L27/0802 , H01L28/20
摘要： The invention provides a voltage regulator. The voltage regulator (100) of the invention includes a comparison circuit (20) and a voltage divider circuit (110). The voltage divider circuit (110) has a PMOS transistor (T6) connected to a voltage source (VDD) and resistors (R1, R2, R3, R4, R5 and R6) serially connected between the transistor (T6) and a reference voltage. A feedback voltage generated from a node (N3) between resistors R4 and R5 is provided to the comparison circuit (20). In addition, a middle voltage (Vm) generated from a node (Nc) of the resistors is provided to a well region, so the parasitic capacitance is reduced.
摘要翻译：本发明提供一种电压调节器。本发明的电压调节器（100）包括比较电路（20）和分压电路（110）。分压器电路（110）具有连接到电压源（VDD）的PMOS晶体管（T6）和串联连接在晶体管（T6）和参考电压之间的电阻器（R1，R2，R3，R4，R5和R6）。从电阻器R4和R5之间的节点（N3）产生的反馈电压被提供给比较电路（20）。此外，从电阻器的节点（Nc）产生的中间电压（Vm）被提供给阱区域，因此寄生电容减小。

6. 发明申请

US20150155045A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20150155045A1
公开(公告)日：2015-06-04
申请号：US14447051
申请日：2014-07-30
申请人： Winbond Electronics Corp.
发明人： Masaru YANO
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459
摘要： A semiconductor storage device restraining the variation in threshold voltage of a memory unit is provided. The steps of the programming method for a flash memory include: setting a bit line to a program voltage or a program-protection voltage; applying a program pulse to the selected page; and verifying the programming of the selected page. Also, the steps further include: when the verification result indicates that there is a failed-shift memory cell which was passed previously but is failed presently, setting the voltage of the bit line of the failed shift memory to a mitigation voltage for mitigating the voltage of the next program pulse.
摘要翻译：提供抑制存储器单元的阈值电压变化的半导体存储装置。闪存的编程方法的步骤包括：将位线设置为编程电压或编程保护电压; 将程序脉冲施加到所选择的页面; 并验证所选页面的编程。此外，步骤还包括：当验证结果指示存在先前通过但目前失败的失败移位存储器单元时，将失效移位存储器的位线的电压设置为减轻电压的缓解电压的下一个程序脉冲。

7. 发明申请

US20230118494A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20230118494A1
公开(公告)日：2023-04-20
申请号：US17954655
申请日：2022-09-28
申请人： Winbond Electronics Corp.
发明人： Masaru YANO
IPC分类号： G11C13/00 , G11C16/04 , G11C16/10 , G11C16/26 , G06N3/063 , G06N3/08
摘要： A semiconductor memory device has a NOR-type memory cell array, a crossbar array, an entry gate, and a column selecting/signal processing unit. The crossbar array has a plurality of rows and columns, variable resistor elements formed in intersections of rows and columns respectively. The entry gate arranged between the memory cell array and the crossbar array, connects a selected bit line of the memory cell array to the crossbar array based on a selection signal. The column selecting/signal processing unit has a column writing unit, a column reading unit, and a NOR writing unit. The column writing unit writes data read from the memory cell array to a selected column of the crossbar array. The column reading unit reads data of the selected column of the crossbar array. The NOR writing unit at least writes data read by the column writing unit to the memory cell array.

8. 发明申请

US20180083788A1 SEMICONDUCTOR DEVICE AND SECURITY SYSTEM 审中-公开
公开(公告)号：US20180083788A1
公开(公告)日：2018-03-22
申请号：US15710358
申请日：2017-09-20
申请人： Winbond Electronics Corp.
发明人： Masaru YANO
IPC分类号： H04L9/32 , H04L9/34 , G06F11/07 , G11C7/24
摘要： A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.

9. 发明申请

US20160125947A1 PROGRAMMING METHOD FOR NAND-TYPE FLASH MEMORY 有权
标题翻译： NAND型闪存存储器的编程方法
公开(公告)号：US20160125947A1
公开(公告)日：2016-05-05
申请号：US14926420
申请日：2015-10-29
申请人： Winbond Electronics Corp.
发明人： Masaru YANO
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/10 , G11C16/32
摘要： The invention provides a programming method for a NAND-type flash memory capable of reducing the drop in reliability due to data-rewriting. The programming method includes: when a block program mode is executed to perform programming for a plurality of pages in a block, while the data to be programmed is being loaded into a cache memory; and erasing the selected block; and programming the data to be programmed which is loaded into the cache memory to the erased block.
摘要翻译：本发明提供了一种NAND型闪存的编程方法，能够减少由于数据重写导致的可靠性下降。编程方法包括：当块被编程的数据被加载到高速缓冲存储器中时，执行块编程模式以对块中的多个页执行编程; 并擦除所选择的块; 并将要编程的数据编程到缓存存储器中以被擦除的块。

10. 发明申请

US20140043906A1 SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：半导体存储器件
公开(公告)号：US20140043906A1
公开(公告)日：2014-02-13
申请号：US13744965
申请日：2013-01-18
申请人： Winbond Electronics Corp.
发明人： Masaru YANO
IPC分类号： G11C16/10
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C2216/18
摘要： A flash memory capable of writing or deleting a split block is provided. A flash memory includes a memory array comprising a plurality of blocks, and a word line selection circuit, wherein each of the plurality of blocks is formed by a plurality of cell units in a well. The cell unit comprises N memory cells, a selection transistor coupled to one terminal of the memory cells, a selection transistor coupled to the other terminal of the memory cells, and a dummy selection transistor coupled between the memory cells. The word line selection circuit splits the block into a first block and a second block to use according to the operation of data writing or data deleting.
摘要翻译：提供了能够写入或删除分割块的闪速存储器。闪速存储器包括包括多个块的存储器阵列和字线选择电路，其中多个块中的每一个由阱中的多个单元单元形成。单元单元包括N个存储单元，耦合到存储单元的一个端子的选择晶体管，耦合到存储单元的另一个端子的选择晶体管，以及耦合在存储单元之间的虚拟选择晶体管。字线选择电路根据数据写入或数据删除的操作将块分割成第一块和第二块。

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