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1. 发明授权

US09870828B2 Non-volatile semiconductor memory and erasing method thereof 有权
公开(公告)号：US09870828B2
公开(公告)日：2018-01-16
申请号：US15277992
申请日：2016-09-27
申请人： Winbond Electronics Corp.
发明人： Katsutoshi Suito , Riichiro Shirota
IPC分类号： G11C16/14 , G11C16/34 , G11C16/10 , G11C16/04 , H01L27/11524
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C16/3472 , G11C16/3477 , H01L27/11524
摘要： An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).

2. 发明申请

US20150170748A1 Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current 有权
标题翻译：擦除三维非易失性存储器，具有可控的栅极引入漏极泄漏电流
公开(公告)号：US20150170748A1
公开(公告)日：2015-06-18
申请号：US14631080
申请日：2015-02-25
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/14 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
摘要翻译：用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以从更高的栅极引起的漏极泄漏（GIDL）电流中受益，以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

3. 发明授权

US09019775B2 Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current 有权
标题翻译：擦除具有可控制栅极漏极漏电流的3D非易失性存储器的操作
公开(公告)号：US09019775B2
公开(公告)日：2015-04-28
申请号：US13450313
申请日：2012-04-18
申请人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L Mui
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L Mui
IPC分类号： G11C11/34 , G11C5/02 , G11C16/06 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
摘要翻译：用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以从更高的栅极引起的漏极泄漏（GIDL）电流中受益，以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

4. 发明授权

US07561476B2 Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory 有权
公开(公告)号：US07561476B2
公开(公告)日：2009-07-14
申请号：US11072198
申请日：2005-03-03
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G11C16/04
CPC分类号： G11C16/3472 , G11C16/3468 , G11C16/3481
摘要： Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs reading is connected to a switch which switches an operation voltage applied to a memory cell in accordance with a verify signal Sv, and the verify operation is finished concurrently with having the verify signal Sv switched. By obtaining such circuit construction and simultaneously performing writing/erasing and reading, it becomes possible to perform high-speed verify writing/erasing.

5. 发明授权

US07408804B2 Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells 有权
标题翻译：用于软编程非易失性存储器的系统，其利用存储器单元的子集的单独验证和附加的软编程
公开(公告)号：US07408804B2
公开(公告)日：2008-08-05
申请号：US11296071
申请日：2005-12-06
申请人： Gerrit Jan Hemink , Teruhiko Kamei
发明人： Gerrit Jan Hemink , Teruhiko Kamei
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.
摘要翻译：一组非易失性存储元件被划分为用于软编程的子集，以便更软地编程较慢的软编程元件。整个元素组被软编程，直到被验证为软编程（或直到第一个元素子集被验证为软编程，而不是第二个子集验证）。在集合被验证为软编程之后，元素的第一子集被禁止进一步的软编程，而在第二子元素上执行附加的软编程。第二子集可以包括较慢的软编程元素。然后可以将第二个子集进行软编程验证，同时将第一个子集排除在验证之外。软编程和验证第二个子集可以继续，直到它被验证为软编程。可以使用不同的步长来增加软编程信号的大小，具体取决于软编程和验证哪个子集。

6. 发明授权

US07403428B2 Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells 有权
标题翻译：用于利用改变字线条件擦除非易失性存储器以补偿较慢擦除存储器单元的系统
公开(公告)号：US07403428B2
公开(公告)日：2008-07-22
申请号：US11296032
申请日：2005-12-06
申请人： Masaaki Higashitani
发明人： Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages within a NAND string. After biasing a NAND string for an erase operation and beginning application of the erase voltage pulse, the word lines of one or more interior memory cells can be floated. By floating the selected interior word lines, the peak erase potential created across the tunnel dielectric region of the cells coupled thereto is decreased from its normal level. Consequently, the erase rates of these cells are slowed to substantially match that of the slower erasing end memory cells of the string. Different word lines can be floated at different times to alter the erase behavior of different memory cells by different amounts.
摘要翻译：施加到非易失性存储器系统的存储器单元的电压条件在擦除操作期间被改变，以便等同于被同时擦除的系统的其它存储器单元的选择存储器单元的擦除行为。改变的条件可以补偿NAND串中的电容耦合电压。在对NAND串进行擦除操作并开始施加擦除电压脉冲之后，一个或多个内部存储器单元的字线可以浮置。通过浮动所选择的内部字线，跨越与其耦合的单元的隧道电介质区域产生的峰值擦除电位从其正常水平减小。因此，这些单元的擦除速率减慢到基本上与串的较慢的擦除结束存储单元的擦除速率基本一致。不同的字线可以在不同的时间漂浮，以改变不同存储单元的擦除行为。

7. 发明申请

US20070076465A1 Erase method to reduce erase time and to prevent over-erase 有权
公开(公告)号：US20070076465A1
公开(公告)日：2007-04-05
申请号：US11297085
申请日：2005-12-08
申请人： Chung-Zen Chen , Chung-Shan Kuo
发明人： Chung-Zen Chen , Chung-Shan Kuo
IPC分类号： G11C17/00
CPC分类号： G11C16/3468 , G11C16/16 , G11C16/3472
摘要： An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.

8. 发明申请

US20060221708A1 Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells 有权
标题翻译：使用改变的字线条件来擦除非易失性存储器以补偿较慢的擦除存储器单元
公开(公告)号：US20060221708A1
公开(公告)日：2006-10-05
申请号：US11295755
申请日：2005-12-06
申请人： Masaaki Higashitani
发明人： Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages within a NAND string. After biasing a NAND string for an erase operation and beginning application of the erase voltage pulse, the word lines of one or more interior memory cells can be floated. By floating the selected interior word lines, the peak erase potential created across the tunnel dielectric region of the cells coupled thereto is decreased from its normal level. Consequently, the erase rates of these cells are slowed to substantially match that of the slower erasing end memory cells of the string. Different word lines can be floated at different times to alter the erase behavior of different memory cells by different amounts.
摘要翻译：施加到非易失性存储器系统的存储器单元的电压条件在擦除操作期间被改变，以便等同于被同时擦除的系统的其它存储器单元的选择存储器单元的擦除行为。改变的条件可以补偿NAND串中的电容耦合电压。在对NAND串进行擦除操作并开始施加擦除电压脉冲之后，一个或多个内部存储器单元的字线可以浮置。通过浮动所选择的内部字线，跨越与其耦合的单元的隧道电介质区域产生的峰值擦除电位从其正常水平减小。因此，这些单元的擦除速率减慢到基本上与串的较慢的擦除结束存储单元的擦除速率基本一致。不同的字线可以在不同的时间漂浮，以改变不同存储单元的擦除行为。

9. 发明申请

US20050162908A1 Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory 有权
标题翻译：非易失性存储器，验证方法以及使用非易失性存储器的半导体器件
公开(公告)号：US20050162908A1
公开(公告)日：2005-07-28
申请号：US11072198
申请日：2005-03-03
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3472 , G11C16/3468 , G11C16/3481
摘要： Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs reading is connected to a switch which switches an operation voltage applied to a memory cell in accordance with a verify signal Sv, and the verify operation is finished concurrently with having the verify signal Sv switched. By obtaining such circuit construction and simultaneously performing writing/erasing and reading, it becomes possible to perform high-speed verify writing/erasing.
摘要翻译：提供实现高速验证操作的非易失性存储器。在验证写/擦除期间，同时执行写/擦除和读取。对于执行验证操作的电路，例如，获得了一种结构，其中执行读取的读出放大器（102）的输出连接到根据存储单元切换施加到存储单元的操作电压的开关验证信号Sv，并且验证操作在切换了验证信号Sv的同时完成。通过获得这种电路结构并且同时进行写入/擦除和读取，可以执行高速验证写入/擦除。

10. 发明授权

US06876581B2 Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory 有权
标题翻译：非易失性存储器，验证方法以及使用非易失性存储器的半导体器件
公开(公告)号：US06876581B2
公开(公告)日：2005-04-05
申请号：US10822388
申请日：2004-04-12
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3472 , G11C16/3468 , G11C16/3481
摘要： Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs reading is connected to a switch which switches an operation voltage applied to a memory cell in accordance with a verify signal Sv, and the verify operation is finished concurrently with having the verify signal Sv switched. By obtaining such circuit construction and simultaneously performing writing/erasing and reading, it becomes possible to perform high-speed verify writing/erasing.
摘要翻译：提供实现高速验证操作的非易失性存储器。在验证写/擦除期间，同时执行写/擦除和读取。对于执行验证操作的电路，例如，获得了一种结构，其中执行读取的读出放大器（102）的输出连接到根据存储单元切换施加到存储单元的操作电压的开关验证信号Sv，并且验证操作在切换了验证信号Sv的同时完成。通过获得这种电路结构并且同时进行写入/擦除和读取，可以执行高速验证写入/擦除。

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