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1. 发明授权

US11474555B1 Data-driven platform characteristics capture and discovery for hardware accelerators 有权
公开(公告)号：US11474555B1
公开(公告)日：2022-10-18
申请号：US15684035
申请日：2017-08-23
申请人： Xilinx, Inc.
发明人： Hem C. Neema , Sonal Santan , Julian M. Kain , Stephen P. Rozum , Khang K. Dao , Kyle Corbett
IPC分类号： G06F1/10 , G06F13/10 , G06F13/28 , G06F13/16 , G06F13/40
摘要： An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable region of the acceleration circuit. The software platform includes program code executable by the processing system to read the metadata from the memory of the hardware accelerator.

2. 发明授权

US09792395B1 Memory utilization in a circuit design 有权
公开(公告)号：US09792395B1
公开(公告)日：2017-10-17
申请号：US15013196
申请日：2016-02-02
申请人： Xilinx, Inc.
发明人： Jayaram Pvss , Robert Bellarmin Susai , Khang K. Dao
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.

3. 发明授权

US08813005B1 Debugging using tagged flip-flops 有权
标题翻译：使用标记的触发器进行调试
公开(公告)号：US08813005B1
公开(公告)日：2014-08-19
申请号：US14016941
申请日：2013-09-03
申请人： Xilinx, Inc.
发明人： Khang K. Dao , Kyle Corbett
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Approaches for testing a module of a circuit design include tagging flip-flops in a netlist of the module with respective path names of the flip-flops from a hardware description language specification of the module. In simulating with the netlist, event data are captured to a first file. A process determines whether or not event data in the first file matches event data in a second file of event data. In response to a difference determined between the first file and the second file, an earliest occurrence of an event in the first file having an associated signal value of a first signal that does not match an associated signal value of a corresponding event in the second file is determined. The one of the plurality of flip-flops that output the first signal is determined, and the respective path name of the one flip-flop is output.
摘要翻译：用于测试电路设计的模块的方法包括：根据模块的硬件描述语言规范，将模块的网表中的触发器标记为具有触发器的相应路径名称的网表。在与网表模拟时，将事件数据捕获到第一个文件。进程确定第一文件中的事件数据是否匹配事件数据的第二文件中的事件数据。响应于在第一文件和第二文件之间确定的差异，第一文件中最早出现的事件具有与第二文件中的相应事件的相关信号值不匹配的第一信号的相关信号值决心，决意，决定。确定输出第一信号的多个触发器中的一个，并输出一个触发器的相应路径名。

4. 发明授权

US11204747B1 Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions 有权
公开(公告)号：US11204747B1
公开(公告)日：2021-12-21
申请号：US15786395
申请日：2017-10-17
申请人： Xilinx, Inc.
发明人： Jindrich Zejda , Elliott Delaye , Yongjun Wu , Aaron Ng , Ashish Sirasao , Khang K. Dao , Christopher J. Case
IPC分类号： G06F9/45 , G06F8/41 , G06N3/02 , G06F13/28 , G06F8/30 , G06F9/451 , G06F9/50 , G06F13/362
摘要： Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator that operate on two heterogeneous computing systems. For example, the neural network application may execute on a central processing unit (CPU) in a computing system while the neural network accelerator executes on a FPGA. As a result, when moving a software-hardware boundary between the two heterogeneous systems, changes may be made to both the neural network application (using software code) and to the accelerator (using RTL). The embodiments herein describe a software defined approach where shared interface code is used to express both sides of the interface between the two heterogeneous systems in a single abstraction (e.g., a software class).

5. 发明授权

US10970446B1 Automated pipeline insertion on a bus 有权
公开(公告)号：US10970446B1
公开(公告)日：2021-04-06
申请号：US15988448
申请日：2018-05-24
申请人： Xilinx, Inc.
发明人： Jeffrey H. Seltzer , Khang K. Dao , Sabyasachi Das
IPC分类号： G06F30/3312 , G06F30/34 , G06F30/327 , G06F30/392 , G06F30/394 , G06F30/398 , G06F119/12
摘要： The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.

6. 发明授权

US10819680B1 Interface firewall for an integrated circuit of an expansion card 有权
公开(公告)号：US10819680B1
公开(公告)日：2020-10-27
申请号：US15915981
申请日：2018-03-08
申请人： Xilinx, Inc.
发明人： Sonal Santan , Umang Parekh , Jeffrey H. Seltzer , Khang K. Dao , Kyle Corbett
IPC分类号： H04L29/06 , G06F13/42
摘要： System and method generally relate to protection of a bussed network. In such a system, an access controller is configured for bussed communication via a communication bus to obtain a current transaction. An interface firewall is coupled for bussed communication with the access controller and configured to check for a fault associated with a transfer. A data processing device is coupled for communication with the interface firewall and configured to execute the current transaction to provide the transfer for the interface firewall. The interface firewall is configured to detect the fault associated with the transfer, to block access to the data processing device associated with the fault, and to communicate a blocked status for the data processing device.

7. 发明授权

US11036827B1 Software-defined buffer/transposer for general matrix multiplication in a programmable IC 有权
公开(公告)号：US11036827B1
公开(公告)日：2021-06-15
申请号：US15786346
申请日：2017-10-17
申请人： Xilinx, Inc.
发明人： Jindrich Zejda , Elliott Delaye , Yongjun Wu , Aaron Ng , Ashish Sirasao , Khang K. Dao
IPC分类号： G06F17/16 , G06F7/78 , G06F9/30
摘要： Methods and apparatus are described for simultaneously buffering and reformatting (e.g., transposing) a matrix for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). Examples of the present disclosure increase the effective double data rate (DDR) memory throughput for streaming data into GEMM digital signal processing (DSP) engine multifold, as well as eliminate slow data reformatting on a host central processing unit (CPU). This may be accomplished through software-defined (e.g., C++) data structures and access patterns that result in hardware logic that simultaneously buffers and reorganizes the data to achieve linear DDR addressing.

8. 发明授权

US10802995B2 Unified address space for multiple hardware accelerators using dedicated low latency links 有权
公开(公告)号：US10802995B2
公开(公告)日：2020-10-13
申请号：US16046602
申请日：2018-07-26
申请人： Xilinx, Inc.
发明人： Sarabjeet Singh , Hem C. Neema , Sonal Santan , Khang K. Dao , Kyle Corbett , Yi Wang , Christopher J. Case
IPC分类号： G06F9/38 , G06F13/16 , G06F9/46 , G06F12/0873 , G06F12/1045 , G06F12/1081
摘要： A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

9. 发明申请

US20200081850A1 UNIFIED ADDRESS SPACE FOR MULTIPLE HARDWARE ACCELERATORS USING DEDICATED LOW LATENCY LINKS 审中-公开
公开(公告)号：US20200081850A1
公开(公告)日：2020-03-12
申请号：US16046602
申请日：2018-07-26
申请人： Xilinx, Inc.
发明人： Sarabjeet Singh , Hem C. Neema , Sonal Santan , Khang K. Dao , Kyle Corbett , Yi Wang , Christopher J. Case
IPC分类号： G06F13/16 , G06F12/1045 , G06F12/0873 , G06F12/1081 , G06F9/46
摘要： A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

10. 发明授权

US10346572B1 Inclusion and configuration of a transaction converter circuit block within an integrated circuit 有权
公开(公告)号：US10346572B1
公开(公告)日：2019-07-09
申请号：US15424684
申请日：2017-02-03
申请人： Xilinx, Inc.
发明人： Kyle Corbett , Khang K. Dao
IPC分类号： G06F17/50
摘要： A method of circuit design can include detecting, using a processor, a transactional inefficiency within trace data including transactions involving a first circuit block of a circuit design and, in response to the detecting, generating a modified version of the circuit design by including a transaction converter circuit block within the circuit design. The transaction converter circuit block can be coupled to the first circuit block and can be adapted to correct the transactional inefficiency.

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