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1. 发明授权

US10699053B1 Timing optimization of memory blocks in a programmable IC 有权
公开(公告)号：US10699053B1
公开(公告)日：2020-06-30
申请号：US15873724
申请日：2018-01-17
申请人： Xilinx, Inc.
发明人： Zhiyong Wang , Ruibing Lu , Lin Chai , Sabyasachi Das
IPC分类号： G06F30/398 , G06F30/34 , G06F30/392 , G06F30/394 , G06F30/3312 , G06F30/39 , G06F30/327 , G06F119/12
摘要： Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.

2. 发明授权

US10528697B1 Timing-closure methodology involving clock network in hardware designs 有权
公开(公告)号：US10528697B1
公开(公告)日：2020-01-07
申请号：US15818436
申请日：2017-11-20
申请人： Xilinx, Inc.
发明人： Wei Chen , Xiaojian Yang , Sabyasachi Das
IPC分类号： G06F17/50
摘要： Embodiments disclosed herein describe techniques for moving nets between a source and a plurality of sinks in a design of an integrated circuit from a data network to a clock network. In one embodiment, the clock network propagates clock signals or timing signals throughout the integrated circuit while the data network transmits data signals between circuitry in the integrated circuit. In one embodiment, the clock network has a predefined number of clock signal nets which can be assigned to carry clock signals to circuit logic in the integrated circuit. However, some of the clock signal nets may be unused. In one embodiment, a design application identifies candidate sinks which have positive slack. If using the clock network to couple the sink to the source satisfies predetermined timing requirements, then the design change is committed.

3. 发明申请

US20180203956A1 NEURAL NETWORK BASED PHYSICAL SYNTHESIS FOR CIRCUIT DESIGNS 审中-公开
公开(公告)号：US20180203956A1
公开(公告)日：2018-07-19
申请号：US15407875
申请日：2017-01-17
申请人： Xilinx, Inc.
发明人： Aaron Ng , Sabyasachi Das , Prabal Basu
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F17/5068 , G06F17/5081 , G06F2217/78 , G06F2217/84
摘要： Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

4. 发明授权

US08984462B1 Physical optimization for timing closure for an integrated circuit 有权
标题翻译：用于集成电路的时序闭合的物理优化
公开(公告)号：US08984462B1
公开(公告)日：2015-03-17
申请号：US14249601
申请日：2014-04-10
申请人： Xilinx, Inc.
发明人： Sabyasachi Das , Ruibing Lu , Zhiyong Wang , Aman Gayasen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/84
摘要： Physical optimization for timing closure for an integrated circuit includes processing a circuit design at least partially through a design flow to a late stage of the design flow. Using a processor, a baseline delay is calculated for each of a plurality of paths of the circuit design. A slack for each of the plurality of paths is determined. Physical optimization further includes selecting a path of the circuit design that meets a selection criterion according, at least in part, to the slack of the path, applying, using the processor, a physical optimization to the selected path resulting in an optimized path, and calculating a delay of the optimized path. The optimized path is incorporated into the circuit design only responsive to determining that the delay of the optimized path is less than the baseline delay of the selected path.
摘要翻译：用于集成电路的时序闭合的物理优化包括至少部分地通过设计流处理电路设计到设计流程的后期阶段。使用处理器，为电路设计的多个路径中的每一个计算基线延迟。确定多个路径中的每一个的松弛。物理优化进一步包括至少部分地根据路径的松弛来选择满足选择标准的电路设计的路径，使用处理器对所选择的路径应用物理优化，得到优化的路径，以及计算优化路径的延迟。优化的路径被合并到电路设计中，仅响应于确定优化路径的延迟小于所选路径的基线延迟。

5. 发明授权

US10970446B1 Automated pipeline insertion on a bus 有权
公开(公告)号：US10970446B1
公开(公告)日：2021-04-06
申请号：US15988448
申请日：2018-05-24
申请人： Xilinx, Inc.
发明人： Jeffrey H. Seltzer , Khang K. Dao , Sabyasachi Das
IPC分类号： G06F30/3312 , G06F30/34 , G06F30/327 , G06F30/392 , G06F30/394 , G06F30/398 , G06F119/12
摘要： The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.

6. 发明授权

US10068045B1 Programmable logic device design implementations with multiplexer transformations 有权
公开(公告)号：US10068045B1
公开(公告)日：2018-09-04
申请号：US15374994
申请日：2016-12-09
申请人： Xilinx, Inc.
发明人： Sabyasachi Das , Chiwei Huang
IPC分类号： G06F17/50
摘要： A programmable logic design is generated for a programmable logic device (PLD) containing configurable logic blocks (CLBs) each having a plurality of multiplexers and look-up-table (LUT) circuits. A first subset of multiplexers are identified from the plurality of multiplexers based upon an analysis of design definitions for input signals of the plurality of multiplexers. The first subset of multiplexers are transformed into LUT logic. Configuration data is generated that is designed to be loaded into the PLD to configure the CLBs. The configuration data includes the LUT logic.

7. 发明授权

US09773083B1 Post-placement and pre-routing processing of critical paths in a circuit design 有权
公开(公告)号：US09773083B1
公开(公告)日：2017-09-26
申请号：US15069598
申请日：2016-03-14
申请人： Xilinx, Inc.
发明人： Sabyasachi Das , Zhiyong Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5072 , G06F2217/84
摘要： Aspects of processing a circuit design include synthesizing the circuit design and placing elements of the synthesized circuit design. After placing and before routing, respective delay values and slacks are determined. A first path having a most negative slack is determined and a first group of candidate paths is selected. The first group of candidate paths is a subset of critical paths of the circuit design, and the first group of candidate paths have delay values within a threshold range of delay values from the delay value of the first path. The first group of candidate paths are modified to reduce the respective delay values and a second group of candidate paths is selected. The second group of candidate paths have circuit structures that match selected circuit structures and are modified to reduce the respective delay values. A critical path having a most negative slack is iteratively selected and modified to reduce the respective delay value.

8. 发明授权

US09613173B1 Interactive multi-step physical synthesis 有权
公开(公告)号：US09613173B1
公开(公告)日：2017-04-04
申请号：US14873072
申请日：2015-10-01
申请人： Xilinx, Inc.
发明人： Rajat Aggarwal , Zhiyong Wang , Ruibing Lu , Sabyasachi Das
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/78 , G06F2217/84
摘要： A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

9. 发明授权

US10303648B1 Logical and physical optimizations for partial reconfiguration design flow 有权
公开(公告)号：US10303648B1
公开(公告)日：2019-05-28
申请号：US15600534
申请日：2017-05-19
申请人： Xilinx, Inc.
发明人： Sabyasachi Das , Zhiyong Wang , Niyati Shah
IPC分类号： G06F17/50 , G06F17/00 , G06F15/00 , G06F9/30 , G06F15/78 , G06F9/38 , G06F15/80 , G06F15/76
摘要： Implementing a partial reconfiguration design flow can include determining an interface net connecting static circuitry and a first reconfigurable module of a circuit design, performing, using a processor, a logical optimization on first circuitry of the static circuitry that is entirely external to the first reconfigurable module and on second circuitry entirely within the reconfigurable module, and excluding the interface net from processing using the logical optimization.

10. 发明授权

US10192016B2 Neural network based physical synthesis for circuit designs 有权
公开(公告)号：US10192016B2
公开(公告)日：2019-01-29
申请号：US15407875
申请日：2017-01-17
申请人： Xilinx, Inc.
发明人： Aaron Ng , Sabyasachi Das , Prabal Basu
IPC分类号： G06F17/50
摘要： Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

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