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1. 发明申请

US20080195822A1 PILOT PLACEMENT FOR NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的引导放置
公开(公告)号：US20080195822A1
公开(公告)日：2008-08-14
申请号：US12029134
申请日：2008-02-11
申请人： Xueshi Yang , Zining Wu , Pantas Sutardja
发明人： Xueshi Yang , Zining Wu , Pantas Sutardja
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括与包括B个存储器块的存储器阵列通信的格式模块，每个B存储器块包括P个物理页面和Q个逻辑页面。格式化模块选择X个预定位置以在每个B存储块中写入导频数据和读回导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与读回导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

2. 发明授权

US08031526B1 Write pre-compensation for nonvolatile memory 有权
标题翻译：写入非易失性存储器的预补偿
公开(公告)号：US08031526B1
公开(公告)日：2011-10-04
申请号：US12196819
申请日：2008-08-22
申请人： Zining Wu , Xueshi Yang , Pantas Sutardja
发明人： Zining Wu , Xueshi Yang , Pantas Sutardja
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2029/1204
摘要： A memory integrated circuit (IC) includes an input that receives data for programming a target cell to a state. The memory IC further includes a programming module that determines a programming value for programming the target cell to the state based on the state and states of C cells that are adjacent to the target cell. The target cell and the C cells each store K bits per cell, where C and K are integers greater than or equal to 1.
摘要翻译：存储器集成电路（IC）包括接收用于将目标单元编程为状态的数据的输入。存储器IC还包括编程模块，其基于与目标单元相邻的C单元的状态和状态，确定用于将目标单元编程为状态的编程值。目标单元和C单元每个存储每个单元的K位，其中C和K是大于或等于1的整数。

3. 发明授权

US08407559B2 Monitoring memory 有权
标题翻译：监控内存
公开(公告)号：US08407559B2
公开(公告)日：2013-03-26
申请号：US12476683
申请日：2009-06-02
申请人： Xueshi Yang , Zining Wu , Pantas Sutardja
发明人： Xueshi Yang , Zining Wu , Pantas Sutardja
IPC分类号： G11C29/00
CPC分类号： G11C16/3404
摘要： Devices, systems, methods, and other embodiments associated with monitoring memory are described. In one embodiment, a method determines a first data quality associated with a set of data stored in flash memory. Based, at least in part, on the first data quality, the flash memory is controlled to correct the set of data to produce a corrected set of data. The corrected set of data is reprogrammed into the flash memory.
摘要翻译：描述了与监视存储器相关联的设备，系统，方法和其他实施例。在一个实施例中，一种方法确定与存储在闪速存储器中的一组数据相关联的第一数据质量。至少部分地基于第一数据质量，控制闪速存储器以校正该组数据以产生校正的数据集。校正的数据组被重新编程到闪存中。

4. 发明授权

US08358541B1 Write pre-compensation for nonvolatile memory 有权
标题翻译：写入非易失性存储器的预补偿
公开(公告)号：US08358541B1
公开(公告)日：2013-01-22
申请号：US13251822
申请日：2011-10-03
申请人： Zining Wu , Xueshi Yang , Pantas Sutardja
发明人： Zining Wu , Xueshi Yang , Pantas Sutardja
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2029/1204
摘要： A system including a programming module and an interference module. The programming module is configured to determine a programming value to which a state of a target cell is to be programmed, wherein the programming value is determined based on states of one or more cells near the target cell. The interference module is configured to generate interference values based on (i) the state of the target cell and (ii) the states of the one or more cells near the target cell. The programming module is further configured to determine the programming value based on at least one of the interference values selected according to (i) the state of the target cell and (ii) the states of the one or more cells near the target cell.
摘要翻译：一种包括编程模块和干扰模块的系统。编程模块被配置为确定要编程目标单元的状态的编程值，其中基于目标单元附近的一个或多个单元的状态来确定编程值。干扰模块被配置为基于（i）目标小区的状态和（ii）目标小区附近的一个或多个小区的状态来产生干扰值。编程模块还被配置为基于根据（i）目标小区的状态选择的干扰值和（ii）目标小区附近的一个或多个小区的状态中的至少一个来确定编程值。

5. 发明授权

US08316206B2 Pilot placement for non-volatile memory 有权
标题翻译：非易失性存储器的飞行员安置
公开(公告)号：US08316206B2
公开(公告)日：2012-11-20
申请号：US12029134
申请日：2008-02-11
申请人： Xueshi Yang , Zining Wu , Pantas Sutardja
发明人： Xueshi Yang , Zining Wu , Pantas Sutardja
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括与包括B个存储器块的存储器阵列通信的格式模块，每个B存储器块包括P个物理页面和Q个逻辑页面。格式化模块选择X个预定位置以在每个B存储块中写入导频数据和读回导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与读回导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

6. 发明授权

US09048879B1 Error correction system using an iterative product code 有权
标题翻译：纠错系统使用迭代产品代码
公开(公告)号：US09048879B1
公开(公告)日：2015-06-02
申请号：US13586710
申请日：2012-08-15
申请人： Shaohua Yang , Zining Wu , Gregory Burd , Xueshi Yang , Hongwei Song , Nedeljko Varnica
发明人： Shaohua Yang , Zining Wu , Gregory Burd , Xueshi Yang , Hongwei Song , Nedeljko Varnica
IPC分类号： H03M13/29 , H04L1/00
CPC分类号： H03M13/2945 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/23 , H03M13/2909 , H03M13/2957 , H03M13/3746 , H04L1/0065
摘要： An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.
摘要翻译：纠错系统包括使用交织分量代码和嵌入奇偶校验分量代码的迭代代码。在一些实施例中，在传输侧，在输入节点处接收的输入信号基于交织的代码进行编码，该代码编码输入数据的交错版本以产生第一组码字。第一组码字的至少一部分优选地被划分为多个符号，这些符号基于嵌入的奇偶校验码被编码以提供编码数据。类似地，在一些实施例中，在接收侧，检测所接收的数据以产生检测到的信息和软输出。检测到的信息根据嵌入的奇偶校验码进行解码以获得解码的信息。解码的信息优选地与其他软信息一起被交织的解码器使用以产生用于偏置随后的解码迭代的可靠性度量。

7. 发明授权

US08635508B2 Systems and methods for performing concatenated error correction 有权
标题翻译：用于执行连接纠错的系统和方法
公开(公告)号：US08635508B2
公开(公告)日：2014-01-21
申请号：US13604391
申请日：2012-09-05
申请人： Xueshi Yang , Zining Wu , Seo-How Low
发明人： Xueshi Yang , Zining Wu , Seo-How Low
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , G06F11/1072 , H03M13/152 , H03M13/2903 , H03M13/2906
摘要： A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.
摘要翻译：提供了一种用于执行串联纠错的系统和方法。在一个实施方式中，用于编码数据的装置包括外编码器，用于产生与所接收的输入数据相对应的代码字，以及奇偶校验电路来计算数据的逻辑单元的奇偶校验，数据的逻辑单元从代码字获得并具有第一个逻辑单元。该装置还包括内编码器，用于基于与第一逻辑单元相对应的第一奇偶校验位产生第一逻辑单元的纠错位，并将误差校正位插入第一逻辑单元。

8. 发明授权

US08406048B2 Accessing memory using fractional reference voltages 有权
$Accessing memory using fractional reference voltages$
标题翻译：使用分数参考电压访问存储器
公开(公告)号：US08406048B2
公开(公告)日：2013-03-26
申请号：US12535987
申请日：2009-08-05
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/34 , G11C11/5642 , G11C16/10 , G11C16/28 , G11C2211/5634
摘要： Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results.
摘要翻译：描述了使用分数参考电压访问存储器的设备，系统，方法和其他实施例。在一个实施例中，一种装置包括比较逻辑。比较逻辑将存储器单元的阈值电压与至少一对分数参考电压进行比较以产生比较结果。该装置包括至少部分地基于比较结果来确定存储器单元的位值的读取逻辑。

9. 发明授权

US08331169B1 Determining threshold voltage distribution in flash memory 有权
标题翻译：确定闪存中的阈值电压分布
公开(公告)号：US08331169B1
公开(公告)日：2012-12-11
申请号：US13323787
申请日：2011-12-12
申请人： Xueshi Yang , Zining Wu , Gregory Burd
发明人： Xueshi Yang , Zining Wu , Gregory Burd
IPC分类号： G11C7/00
CPC分类号： G11C16/26 , G11C16/06 , G11C16/3404
摘要： Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash memory cells having threshold voltages that fall within each bin of a plurality of bins is determined. The plurality of bins each represent a plurality of threshold voltage ranges. A threshold voltage distribution of the plurality of flash memory cells is calculated based at least in part on the number of flash memory cells that fall into each of the bins.
摘要翻译：用于将多个快闪存储器单元的阈值电压与多个参考电压进行比较的方法，装置和系统。确定具有落在多个箱体的每个箱体内的阈值电压的多个闪存单元。多个箱体各自表示多个阈值电压范围。至少部分地基于落入每个仓的闪存单元的数量来计算多个快闪存储单元的阈值电压分布。

10. 发明授权

US08085605B2 Sequence detection for flash memory with inter-cell interference 有权
标题翻译：具有小区间干扰的闪存的序列检测
公开(公告)号：US08085605B2
公开(公告)日：2011-12-27
申请号：US12191616
申请日：2008-08-14
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： G11C7/18
CPC分类号： G11C16/04 , G11C7/02 , G11C7/14 , G11C16/06 , G11C16/26 , G11C16/3418 , G11C16/3422
摘要： A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells.
摘要翻译：存储器集成电路（IC）包括读取模块和序列检测器模块。读取模块读取沿着位线和字线中的一个位置的S个存储单元（单元），并产生S个读取信号，其中S是大于1的整数。序列检测器模块基于S个读取信号来检测数据序列和参考信号。数据序列包括存储在S单元中的数据。每个参考信号包括与S个小区中的一个相关联的无干扰信号和与S个小区之一相邻的S个小区中的另一个的干扰信号。

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